公开(公告)号：US08688961B2

公开(公告)日：2014-04-01

申请号：US13427045

申请日：2012-03-22

Applicant: Matthew Accapadi ,  Robert H. Bell, Jr. ,  Hong Lam Hua ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas

Inventor： Matthew Accapadi ,  Robert H. Bell, Jr. ,  Hong Lam Hua ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas

IPC: G06F9/30

CPC classification number: G06F9/505 ,  G06F12/0862 ,  G06F2209/503 ,  G06F2212/6026

Abstract: A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.

公开(公告)号：US08688960B2

公开(公告)日：2014-04-01

申请号：US12905176

申请日：2010-10-15

Applicant: Matthew Accapadi ,  Robert H. Bell, Jr. ,  Hong Lam Hua ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas

Inventor： Matthew Accapadi ,  Robert H. Bell, Jr. ,  Hong Lam Hua ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas

IPC: G06F9/30

CPC classification number: G06F9/505 ,  G06F12/0862 ,  G06F2209/503 ,  G06F2212/6026

Abstract: A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.

Abstract translation: 公开了用于管理虚拟机环境中的预取流的方法，系统和计算机可用介质。 包括专用寄存器（SPR）和多个第一预取引擎的第一核心中的编译应用代码启动预取流请求。 如果由于第一预取引擎不可用而不能启动预取流请求，则在SPR中设置指示预取流调度故障的指示符位，导致管理程序中断预取流请求的执行。 管理程序然后调用其关联的操作系统（OS），其确定包括多个第二预取引擎的第二核的预取引擎可用性。 如果第二预取引擎可用，则OS将预取流请求从第一核心迁移到第二核心，其中它在可用的第二预取引擎上启动。

公开(公告)号：US08677371B2

公开(公告)日：2014-03-18

申请号：US12650909

申请日：2009-12-31

Applicant: Diane G. Flemming ,  William A. Maron ,  Ram Raghavan ,  Satya Prakash Sharma ,  Mysore S. Srinivas

Inventor： Diane G. Flemming ,  William A. Maron ,  Ram Raghavan ,  Satya Prakash Sharma ,  Mysore S. Srinivas

IPC: G06F9/46 ,  G06F1/00 ,  G06F13/00

CPC classification number: G06F9/5077

Abstract: Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.

Abstract translation: 实现功能以确定系统的多个多核处理单元根据多个操作性能模式来配置。 确定多个操作性能模式中的第一个满足与系统的第一逻辑分区的第一工作负载相对应的第一性能标准。 因此，第一逻辑分区与根据第一操作性能模式配置的多个多核处理单元的第一组相关联。 确定多个操作性能模式中的第二个满足与系统的第二逻辑分区的第二工作负载相对应的第二性能标准。 因此，第二逻辑分区与根据第二操作性能模式配置的多个多核处理单元的第二组关联。

公开(公告)号：US20120216214A1

公开(公告)日：2012-08-23

申请号：US13458769

申请日：2012-04-27

Applicant: Diane G. Flemming ,  William A. Maron ,  Ram Raghavan ,  Satya Prakash Sharma ,  Mysore S. Srinivas

Inventor： Diane G. Flemming ,  William A. Maron ,  Ram Raghavan ,  Satya Prakash Sharma ,  Mysore S. Srinivas

IPC: G06F9/46

CPC classification number: G06F9/5077

Abstract: Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.

Abstract translation: 实现功能以确定系统的多个多核处理单元根据多个操作性能模式来配置。 确定多个操作性能模式中的第一个满足与系统的第一逻辑分区的第一工作负载相对应的第一性能标准。 因此，第一逻辑分区与根据第一操作性能模式配置的多个多核处理单元的第一组相关联。 确定多个操作性能模式中的第二个满足与系统的第二逻辑分区的第二工作负载相对应的第二性能标准。 因此，第二逻辑分区与根据第二操作性能模式配置的多个多核处理单元的第二组相关联。

公开(公告)号：US20120180052A1

公开(公告)日：2012-07-12

申请号：US13427045

申请日：2012-03-22

Applicant: Matthew Accapadi ,  Robert H. Bell, JR. ,  Hong L. Hua ,  Ram Raghavan ,  Mysore S. Srinivas

Inventor： Matthew Accapadi ,  Robert H. Bell, JR. ,  Hong L. Hua ,  Ram Raghavan ,  Mysore S. Srinivas

IPC: G06F9/455

CPC classification number: G06F9/505 ,  G06F12/0862 ,  G06F2209/503 ,  G06F2212/6026

Abstract: A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.

Abstract translation: 公开了用于管理虚拟机环境中的预取流的方法，系统和计算机可用介质。 包括专用寄存器（SPR）和多个第一预取引擎的第一核心中的编译应用代码启动预取流请求。 如果由于第一预取引擎不可用而不能启动预取流请求，则在SPR中设置指示预取流调度故障的指示符位，导致管理程序中断预取流请求的执行。 管理程序然后调用其关联的操作系统（OS），其确定包括多个第二预取引擎的第二核心的预取引擎可用性。 如果第二预取引擎可用，则OS将预取流请求从第一核心迁移到第二核心，其中它在可用的第二预取引擎上启动。

公开(公告)号：US08180941B2

公开(公告)日：2012-05-15

申请号：US12631407

申请日：2009-12-04

Applicant: Wen-Tzer T. Chen ,  Charles R. Johns ,  Ram Raghavan ,  Andrew H. Wottreng

Inventor： Wen-Tzer T. Chen ,  Charles R. Johns ,  Ram Raghavan ,  Andrew H. Wottreng

IPC: G06F13/00 ,  G06F13/368 ,  G06F12/00 ,  G06F13/14

CPC classification number: G06F13/362

Abstract: Mechanisms for priority control in resource allocation is provided. With these mechanisms, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.

Abstract translation: 提供资源分配优先控制机制。 利用这些机制，当单元向令牌管理器发出请求时，该单元识别其请求的优先级以及它希望访问的资源和单元的资源访问组（RAG）。 该信息用于设置与请求中标识的资源，优先级和RAG相关联的存储设备的值。 当令牌管理器生成并向RAG授予令牌时，根据在与资源和RAG相关联的存储设备中标识的未决请求的优先级，将令牌授予RAG内的单元。 优先级指针用于在资源的RAG内提供高优先级请求和低优先级请求之间的循环公平性方案。

公开(公告)号：US20120096241A1

公开(公告)日：2012-04-19

申请号：US12905208

申请日：2010-10-15

Applicant: Robert H. Bell, JR. ,  Hong L. Hua ,  Ram Raghavan ,  Mysore S. Srinivas

Inventor： Robert H. Bell, JR. ,  Hong L. Hua ,  Ram Raghavan ,  Mysore S. Srinivas

IPC: G06F9/30

CPC classification number: G06F9/30054 ,  G06F9/30185 ,  G06F9/3802

Abstract: A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

公开(公告)号：US08131974B2

公开(公告)日：2012-03-06

申请号：US12105427

申请日：2008-04-18

Applicant: Richard Nicholas ,  Ram Raghavan ,  Eric E. Retter ,  Jeffrey A. Stuecheli

Inventor： Richard Nicholas ,  Ram Raghavan ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC: G06F12/00 ,  G06F9/26 ,  G06F9/34

CPC classification number: G06F12/0862 ,  G06F12/0831 ,  G06F2212/507 ,  G06F2212/6022 ,  G06F2212/6024 ,  Y02D10/13

Abstract: An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.

Abstract translation: 提供了可以使用诸如存储器控制器中的空闲有限状态机（FSM）的寄存器的空闲命令处理资源来实现的访问推测预测器。 访问推测预测器可以基于针对数据请求所针对的存储区域存储的历史信息来预测是否对数据处理系统的主存储器执行针对数据请求的数据的推测检索。 特别地，可以从数据请求中提取第一地址，并与存储在存储器控制器的多个FSM的地址寄存器中的第二地址相关联的存储器区域进行比较。 可以选择其存储区域包括第一地址的FSM。 可以从所选择的FSM获得用于存储器区域的历史信息。 历史信息可以用于控制是否从主存储器推测性地检索数据请求的数据。

公开(公告)号：US09298458B2

公开(公告)日：2016-03-29

申请号：US13427083

申请日：2012-03-22

Applicant: Robert H. Bell, Jr. ,  Hong L. Hua ,  Ram Raghavan ,  Mysore S. Srinivas

Inventor： Robert H. Bell, Jr. ,  Hong L. Hua ,  Ram Raghavan ,  Mysore S. Srinivas

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30054 ,  G06F9/30185 ,  G06F9/3802

Abstract: A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

公开(公告)号：US08438338B2

公开(公告)日：2013-05-07

申请号：US12856682

申请日：2010-08-15

Applicant: Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

Inventor： Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

IPC: G06F12/02

CPC classification number: G06F12/0811 ,  G06F12/0284 ,  G06F2212/502 ,  G06F2212/604

Abstract: An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.

Abstract translation: 提供了一种方法来识别对应于在计算机系统上运行的不同分区的高速缓存扩展大小。 该方法利用来自系统存储器区域的第一存储器分配来扩展与包括在处理器的硅衬底中的第一处理核心相关联的第一硬件高速缓存，系统存储器区域在硅衬底外部，并且第一存储器分配对应于 多个缓存扩展大小中的一个对应于在计算机系统上运行的分区之一。 该方法进一步扩展与第二处理核心相关联的第二硬件高速缓存，该第二处理核心还包括在处理器的硅衬底中，具有来自系统存储区域的第二存储器分配，其中第二存储器分配对应于对应于不同分区的另一个高速缓存扩展大小 正在由第二处理核心执行。