-
公开(公告)号：US09966770B2
公开(公告)日：2018-05-08
申请号：US15255092
申请日：2016-09-01
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Wei-Hsu Chang , Ta-Yung Yang , Pei Yu Chiang
IPC: H02J7/00
CPC classification number: H02J7/0021 , H02J7/0045 , H02J7/0052 , H02J7/007 , H02J7/0072 , H02J2007/0059 , H02J2007/0062 , H02J2007/0096
Abstract: A charging apparatus includes a power conversion circuit for charging a battery, and a charging control circuit. The battery has a battery net voltage. The charging control circuit includes a conversion control circuit, a sensing circuit and a determining circuit. The conversion control circuit controls the power conversion circuit to generate plural pairs of DC output voltage levels and DC output current levels, wherein each DC output voltage level and its corresponding DC output current level are a voltage-current pair. The sensing circuit senses the DC output voltage levels and/or the DC output current levels. The determining circuit determines the battery net voltage according to plural voltage-current pairs.
-
公开(公告)号：US20250132664A1
公开(公告)日：2025-04-24
申请号：US18409078
申请日：2024-01-10
Applicant: Richtek Technology Corporation
Inventor： Wei-Hsu Chang , Kun-Yu Lin , Jyun-Che Ho
Abstract: A power supply system with power factor correction, includes: an AC rectifier, a power factor correction (PFC) conversion circuit, an asymmetric half-bridge (AHB) flyback converter and a communication protocol power delivery (PD) interface. When a power level of an adapter output power is lower than a power threshold, and a converted voltage of a converted power is higher than a first voltage threshold, the communication protocol PD interface generates a disable signal to disable a PFC conversion of the PFC conversion circuit, when the PFC conversion is disabled, the PFC conversion circuit operates a bypass coupling operation, as thus, the converted voltage is equal to a rectified voltage of a rectified power.
-
公开(公告)号：US12273035B2
公开(公告)日：2025-04-08
申请号：US18186973
申请日：2023-03-21
Applicant: Richtek Technology Corporation
Inventor： Ta-Yung Yang , Wei-Hsu Chang , Kuo-Chi Liu , Chao-Chi Chen
Abstract: A conversion control circuit controls plural stackable sub-converters which are coupled in parallel to generate an output power to a load, the conversion control circuit includes: a current sharing terminal, wherein a current sharing signal is configured to be connected to the current sharing terminals, in parallel, of the plurality of the conversion control circuits; and a current sharing circuit, configured to generate or receive the current sharing signal which is generated according to an output current of the output power; wherein the conversion control circuit adjusts the power stage circuit according to the current sharing signal for current sharing among the plural stackable sub-converters.
-
34.发明公开公开(公告)号：US20240048046A1
公开(公告)日：2024-02-08
申请号：US18349160
申请日：2023-07-09
Applicant: Richtek Technology Corporation
Inventor： Shih-Ho Hsu , Kun-Yu Lin , Wei-Hsu Chang
CPC classification number: H02M1/42 , H02M1/0009 , H02M1/08 , H02M3/156
Abstract: A boost power factor correction circuit includes: a switch and an inductor coupled to each other; a current sensing device generating a current sensing signal according to a current flowing through the switch; a temperature sensing device coupled to the inductor to generate a temperature sensing signal; and a conversion control circuit operating the switch. The conversion control circuit is an integrated circuit and includes: a shared pin coupled to the temperature sensing device and the current sensing device; and a current sensing circuit and a temperature sensing circuit which sense a multipurpose sensing signal through the shared pin. The multipurpose sensing signal is related to the current sensing signal when the switch is ON and related to the temperature sensing signal when the switch is OFF. The temperature sensing signal is related to an input voltage, an output voltage and an electrical parameter of the temperature sensing device.
-
35.发明公开公开(公告)号：US20230148139A1
公开(公告)日：2023-05-11
申请号：US18048066
申请日：2022-10-20
Applicant: Richtek Technology Corporation
Inventor： Wei-Hsu Chang
CPC classification number: H02M1/4233 , H02M1/0009 , H02M1/0058
Abstract: A power factor correction converter includes a power stage circuit, a current sensing circuit and a zero current prediction circuit. The power stage circuit converts a rectified power to an output power. The power stage circuit operates in a boundary conduction mode to correct a power factor of the rectified power. The current sensing circuit senses an inductor current to generate a sensing signal. The zero current prediction circuit controls at least one switch by: generating a second period according to a first period, wherein the first period is between when the sensing signal passes a first threshold and when the sensing signal passes a second threshold; and switching a state of the at least one switch at an end time point of the second period, wherein the end time point corresponds to a zero current time point at which the inductor current reaches zero.
-
Patent Agency Ranking
公开(公告)号：US20230144791A1
公开(公告)日：2023-05-11
申请号：US17937337
申请日：2022-09-30
Applicant: Richtek Technology Corporation
Inventor： Wei-Hsu Chang
IPC: H02M1/42 , H03M1/12 , H02M7/04 , H03K5/1532
CPC classification number: H02M1/4258 , H03M1/12 , H02M7/04 , H03K5/1532
Abstract: A power factor correction converter includes a rectifier, a power factor correction controller, a power stage circuit, and a feedback circuit, wherein the power factor correction converter converts an AC voltage into an output voltage. The power factor correction controller includes an analog-to-digital converter, a digital peak-hold circuit, a reference voltage generator, an error amplifier, and a pulse-width modulation circuit, wherein the power factor correction controller generates a driving signal according to a rectification signal and a feedback signal. The digital peak-hold circuit includes a delay circuit, a digital rising detector, a tracking register, a digital falling detector, and a holding register, wherein the digital peak-hold circuit generates a peak signal according to a digital input signal.
-
公开(公告)号：US11496063B2
公开(公告)日：2022-11-08
申请号：US17356767
申请日：2021-06-24
Applicant: Richtek Technology Corporation
Inventor： Yu-Chang Chen , Wei-Hsu Chang , Kun-Yu Lin , Ta-Yung Yang
Abstract: A flyback converter includes a power transformer, a primary side switch, a secondary side switch and a controller. A secondary side switching signal has an SR pulse for achieving synchronous rectification, and a ZVS pulse for achieving zero voltage switching. The ZVS pulse is enabled according to a first characteristic of a resonance waveform, whereas, a primary side switching signal is enabled according to a second characteristic of resonance waveform. When an output current increases, the primary side switching signal is disabled during an inhibition interval, such that primary side switching signal does not overlap with the ZVS pulse, thereby preventing the primary and secondary side switches from being both conductive simultaneously. The inhibition interval is correlated with a rising edge of the primary side switching signal in a previous switching period and a resonance period of the resonance waveform.
-
公开(公告)号：US11451154B2
公开(公告)日：2022-09-20
申请号：US17334745
申请日：2021-05-30
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Kun-Yu Lin , Tzu-Chen Lin , Wei-Hsu Chang , Ta-Yung Yang
Abstract: A flyback power converter circuit includes: a power transformer, a primary side switch and a conversion control circuit. In a DCM, during a dead time, the conversion control circuit calculates an upper limit frequency corresponding to output current according to a frequency upper limit function, and obtains a frequency upper limit masking period according to a reciprocal of the upper limit frequency, wherein the frequency upper limit masking period is a period starting from when the primary side switch is turned ON. During an upper limit selection period, the conversion control circuit selects a valley among one or more valleys in a ringing signal related to a voltage across the primary side switch as an upper limit locked valley, so that the conversion control circuit once again turns ON the primary side switch at a beginning time point of the upper limit locked valley.
-
公开(公告)号：US20220181987A1
公开(公告)日：2022-06-09
申请号：US17534538
申请日：2021-11-24
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Ta-Yung Yang , Wei-Hsu Chang , Yu-Chang Chen , Tsung-Wei Huang , Shui-Mu Lin
Abstract: A control circuit for controlling a power supply circuit to provide power to a system device which includes a communication circuit includes: a pulse width modulation (PWM) controller configured to switch a transformer of the power supply circuit to generate a first output voltage; and a switched capacitor converter configured to generate a second output voltage according to the first output voltage. The second output voltage provides power to the communication circuit, wherein the communication circuit generates a power saving signal to control the PWM controller and the switched capacitor converter. When the power saving signal is enabled, the first output voltage is decreased and a duty ratio of the switched capacitor converter is increased.
-
公开(公告)号：US11245267B2
公开(公告)日：2022-02-08
申请号：US16850893
申请日：2020-04-16
Applicant: Richtek Technology Corporation
Inventor： Wei-Hsu Chang
Abstract: A battery module for use in a battery system is coupled with other battery modules in the battery system in a daisy-chain configuration. And, the battery module communicates with the other battery modules through a daisy chain according to a communication interface protocol which has a predetermined number of clock pulses. The battery module includes a battery unit and a battery control circuit. When the battery module operates in a bottom mode, the battery control circuit generates an upstream clock output signal which includes the predetermined number of clock pulses plus a number of inserted clock pulses, to compensate a clock difference caused by a propagation delay of the daisy chain, such that the battery module is able to synchronously receive a downstream data signal transmitted from a target module via the daisy chain as the battery module is transmitting an upstream clock output signal.
-
-
-
-
-
-
-
-
-
Search Results
65
records
(took 0.022 seconds)
