公开(公告)号：US07734876B2

公开(公告)日：2010-06-08

申请号：US11560603

申请日：2006-11-16

申请人： James S. Fields, Jr. ,  Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： James S. Fields, Jr. ,  Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F13/00

CPC分类号： G06F12/0833

摘要： In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Within data storage in the data processing system, a data structure indicates a duration of a protection window extension for each of the plurality of agents. Each protection window extension is a period following receipt of a combined response during which an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. Each of the plurality of agents is configured with a duration of a protection window extension by reference to the data structure, and at least two of the agents have protection window extensions of differing durations. The plurality of agents thereafter employ the configured protection window extensions.

摘要翻译： 在数据处理系统中，多个代理之间进行通信。 每个操作包括一个请求和组合的响应，代表对该请求的全系统响应。 在数据处理系统中的数据存储中，数据结构指示多个代理中的每一个的保护窗口扩展的持续时间。 每个保护窗口扩展是接收到组合响应之后的周期，在该周期期间，所述多个代理中的相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。 通过参考数据结构，多个代理中的每一个配置有保护窗口扩展的持续时间，并且至少两个代理具有不同持续时间的保护窗口扩展。 此后，多个代理程序采用配置的保护窗口扩展。

公开(公告)号：US07451277B2

公开(公告)日：2008-11-11

申请号：US11388017

申请日：2006-03-23

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F2212/507

摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping an exclusive access operation, the exclusive access request specifying a target address matching the address tag and indicating a relative domain location of a requester that initiated the exclusive access operation, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within the first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requestor.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态， 存储位置不包含有效数据。 响应于窥探独占访问操作，专用访问请求指定与地址标签匹配的目标地址，并且指示发起独占访问操作的请求者的相对域位置，第一高速缓存存储器从第一数据更新相关性状态字段 - 无效的一致性状态到指示地址标签有效的第二数据无效一致性状态，存储位置不包含有效数据，以及与地址标签相关联的目标存储器块是否被缓存在第一相关域内 基于请求者的相对位置成功完成独占访问操作。

公开(公告)号：US07444494B2

公开(公告)日：2008-10-28

申请号：US11140821

申请日：2005-05-31

申请人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0833 ,  G06F2212/507

摘要： According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.

摘要翻译： 根据数据处理的方法，保持预测器，其指示在数据处理系统的互连上发送的一个或多个先前操作的广播的历史范围。 通过参考预测器预测性地选择后续操作的广播范围。

公开(公告)号：US08347037B2

公开(公告)日：2013-01-01

申请号：US12256002

申请日：2008-10-22

申请人： Guy L. Guthrie ,  Thomas L. Jeremiah ,  William L. McNeil ,  Piyush C. Patel ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Guy L. Guthrie ,  Thomas L. Jeremiah ,  William L. McNeil ,  Piyush C. Patel ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/128 ,  G06F2212/1028 ,  Y02D10/13

摘要： A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, a determination is made whether the memory access request hits or misses in a directory of the lower level victim cache. In response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache. The lower level victim cache preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.

摘要翻译： 数据处理系统包括具有相关联的高级缓存和较低级别的受害缓存的处理器核心。 响应于指定对目标一致性粒子的不修改访问的处理器核心的存储器访问请求，确定存储器访问请求是否在较低级别的受害缓存的目录中命中或丢失。 响应于确定存储器访问请求在数据有效的相干状态中击中较低级别的受害者高速缓存，则较低级别的受害者缓存将存储器访问请求的目标一致性颗粒提供给高级缓存。 如果存储器访问请求是第一类型，则较低级别的受害者缓存在共享相干状态下保留较低级别的受害者缓存中的目标一致性粒子，如果存储器访问请求是第二类型，则使目标一致性粒子无效。

公开(公告)号：US20120203976A1

公开(公告)日：2012-08-09

申请号：US13445010

申请日：2012-04-12

申请人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0817

摘要： A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.

摘要翻译： 数据处理系统至少包括通过互连结构耦合的第一至第三处理节点。 第一处理节点包括主机，能够参与互连操作的多个侦听器，以及接收主机请求的节点接口，并将主机的请求传送到第二处理单元，传送范围限于 第二处理节点。 第二处理节点包括具有目录的节点接口。 第二处理节点的节点接口允许请求继续进行节点传输范围，如果该目录没有指示该请求的目标存储器块不是在第二处理节点中被缓存，并且如果该请求成功 目录指示除第二处理节点之外的请求的目标存储块被缓存。

公开(公告)号：US07831774B2

公开(公告)日：2010-11-09

申请号：US12118238

申请日：2008-05-09

申请人： Robert H. Bell, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Robert H. Bell, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0888 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1032

摘要： A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.

摘要翻译： 用于在LRU受害者选择期间防止选择被删除（D）成员作为LRU受害者的方法和装置。 在针对特定同余类的每个缓存访问期间，从高速缓存目录中的信息识别已删除的高速缓存行。 删除的高速缓存行的位置在LRU受害者选择期间通过高速缓存架构流水线化。 信息被锁存，然后传递给MRU向量生成逻辑。 生成MRU向量并将其传递给MRU更新逻辑，MRU更新逻辑是将删除的成员作为MRU成员进行选择/标记。 使MRU操作仅影响以基于树的结构状态位布置的较低级LRU状态位，使得MRU操作仅在D状态下否定特定成员的选择，而不影响其他成员的LRU受害者选择。

公开(公告)号：US20100153650A1

公开(公告)日：2010-06-17

申请号：US12335809

申请日：2008-12-16

申请人： Guy L. Guthrie ,  Thomas L. Jeremiah ,  William L. McNeil ,  Piyush C. Patel ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Guy L. Guthrie ,  Thomas L. Jeremiah ,  William L. McNeil ,  Piyush C. Patel ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/126 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/0897 ,  Y02D10/13

摘要： A cache memory includes a cache array including a plurality of congruence classes each containing a plurality of cache lines, where each cache line belongs to one of multiple classes which include at least a first class and a second class. The cache memory also includes a cache directory of the cache array that indicates class membership. The cache memory further includes a cache controller that selects a victim cache line for eviction from a congruence class. If the congruence class contains a cache line belonging to the second class, the cache controller preferentially selects as the victim cache line a cache line of the congruence class belonging to the second class based upon access order. If the congruence class contains no cache line belonging to the second class, the cache controller selects as the victim cache line a cache line belonging to the first class based upon access order.

摘要翻译： 高速缓存存储器包括包含多个等同类的高速缓存阵列，每个级别包含多条高速缓存行，其中每条高速缓存行属于至少包括第一类和第二类的多个类中的一个。 缓存存储器还包括指示类成员资格的高速缓存阵列的高速缓存目录。 高速缓冲存储器还包括高速缓存控制器，其选择用于从同余类驱逐的受害缓存行。 如果同余类包含属于第二类的高速缓存行，则高速缓存控制器基于访问顺序优先选择属于第二类的同余类的高速缓存行作为受害缓存行。 如果同余类不包含属于第二类的高速缓存行，则高速缓存控制器基于访问顺序选择属于第一类的高速缓存行作为受害缓存行。

公开(公告)号：US07725619B2

公开(公告)日：2010-05-25

申请号：US11226967

申请日：2005-09-15

申请人： George W. Daly, Jr. ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： George W. Daly, Jr. ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.

摘要翻译： 数据处理系统至少包括具有输入/输出（I / O）控制器的第一处理节点和包括用于存储器的存储器控​​制器的第二处理。 存储器控制器按顺序从I / O控制器接收流水线的第一和第二DMA写入操作，其中第一和第二DMA写操作分别针对第一和第二地址。 响应于第二DMA写入操作，存储器控制器建立与第二地址相关联的域指示符的状态，以指示包括第一处理节点的操作范围。 响应于所述存储器控制器接收到指定所述第二地址并且具有排除所述第一处理节点的范围的数据访问请求，所述存储器控制器基于所述第一处理节点的状态强迫所述数据访问请求被重新发布，所述范围包括所述第一处理节点 与第二个地址关联的域指示符。

公开(公告)号：US07254694B2

公开(公告)日：2007-08-07

申请号：US11055297

申请日：2005-02-10

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F15/16

CPC分类号： G06F13/385 ,  G06F9/546

摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts requests received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units. The interconnect logic includes a partial response data structure including a plurality of entries each associating a partial response field with a plurality of flags respectively associated with each processing unit containing a snooper from which that processing unit will receive a partial response. The interconnect logic accumulates partial responses of processing units by reference to the partial response field to obtain an accumulated partial response, and when the plurality of flags indicate that all processing units from which partial responses are expected have returned a partial response, outputs the accumulated partial response.

摘要翻译： 数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。 多个处理单元中的每一个包括互连逻辑，其耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个的接收的请求广播到多个处理单元中的一个或多个 处理单位。 互连逻辑包括部分响应数据结构，其包括多个条目，每个条目将部分响应字段与分别与包含窥探者的每个处理单元相关联的多个标志相关联，该处理单元将从该处理单元接收部分响应。 互连逻辑通过参考部分响应字段积累处理单元的部分响应以获得累积的部分响应，并且当多个标志指示预期部分响应的所有处理单元已经返回部分响应时，输出累积的部分响应 响应。

公开(公告)号：US08504779B2

公开(公告)日：2013-08-06

申请号：US13445010

申请日：2012-04-12

申请人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0817

摘要： A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.

摘要翻译： 数据处理系统至少包括通过互连结构耦合的第一至第三处理节点。 第一处理节点包括主机，能够参与互连操作的多个侦听器，以及接收主机请求的节点接口，并将主机的请求传送到第二处理单元，传送范围限于 第二处理节点。 第二处理节点包括具有目录的节点接口。 第二处理节点的节点接口允许请求继续进行节点传输范围，如果该目录没有指示该请求的目标存储器块不是在第二处理节点中被缓存，并且如果该请求成功 目录指示除第二处理节点之外的请求的目标存储块被缓存。