公开(公告)号：US5404473A

公开(公告)日：1995-04-04

申请号：US204612

申请日：1994-03-01

申请人： David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Lawrence O. Smith, III ,  Michael M. Hancock ,  Beth Schultz

发明人： David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Lawrence O. Smith, III ,  Michael M. Hancock ,  Beth Schultz

IPC分类号： G06F9/308 ,  G06F9/32 ,  G06F9/38 ,  G06F13/00

CPC分类号： G06F9/30018 ,  G06F9/325 ,  G06F9/3842

摘要： In a pipelined processor, an apparatus for handling string operations. When a string operation is received by the processor, the length of the string as specified by the programmer is stored in a register. Next, an instruction sequencer issues an instruction that computes the register value minus a pre-determined number of iterations to be issued into the pipeline. Following the instruction, the pre-determined number of iterations are issued to the pipeline. When the instruction returns with the calculated number, the instruction sequencer then knows exactly how many iterations should be executed. Any extra iterations that had initially been issued are canceled by the execution unit, and additional iterations are issued as necessary. A loop counter in the instruction sequencer is used to track the number of iterations.

摘要翻译： 在流水线处理器中，用于处理字符串操作的装置。 当处理器接收到字符串操作时，由编程器指定的字符串的长度存储在寄存器中。 接下来，指令定序器发出计算寄存器值减去要发布到流水线中的预定数量的迭代的指令。 按照该指令，将预先确定的迭代次数发布到流水线。 当指令以计算出的数字返回时，指令定序器将准确地知道应该执行多少次迭代。 最初发布的任何额外的迭代将被执行单元取消，并根据需要发出额外的迭代。 指令定序器中的循环计数器用于跟踪迭代次数。

公开(公告)号：US5604877A

公开(公告)日：1997-02-18

申请号：US176065

申请日：1994-01-04

申请人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani K. Gupta ,  Michael A. Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

发明人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani K. Gupta ,  Michael A. Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

IPC分类号： G06F9/38 ,  G06F9/42

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/4426

摘要： A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the instruction stream. The first stage stores a return address in a return register when a Call Subroutine instruction is predicted. The first stage predicts a return to the return address in the return register when a Return From Subroutine instruction is predicted. A second stage decodes each Call Subroutine and Return From Subroutine instruction in order to maintain a Return Stack Buffer that stores a stack of return addresses. Each time the second stage decodes a Call Subroutine instruction, a return address is pushed onto the Return Stack Buffer. Correspondingly, each time the second stage decodes a Return From Subroutine instruction, a return address is popped off of the Return Stack Buffer. The second stage verifies predictions made by the first stage and predicts return addresses for Return From Subroutine instructions that were not predicted by the first stage. A third stage executes Return From Subroutine instructions such that the predictions are verified. Finally, a fourth stage retires Return From Subroutine instructions and ensures that no instructions fetch after a mispredicted return address are committed into permanent state.

摘要翻译： 公开了一种用于解决计算机处理器中的子程序返回指令的方法和装置。 该方法和设备分四个阶段解析子程序指令。 第一阶段预测指令流中的调用子程序指令和子程序返回指令。 当预测一个调用子程序指令时，第一阶段将返回地址存储在一个返回寄存器中。 第一阶段预测当返回从子程序指令被预测时返回寄存器中的返回地址。 第二阶段解码每个调用子程序和从子程序返回指令，以便维护一个存储一堆返回地址的返回栈缓冲区。 每次第二阶段解码一个调用子程序指令时，一个返回地址被推到返回栈缓冲区上。 相应地，每次第二级解码从子程序返回指令时，返回地址从返回堆栈缓冲区中弹出。 第二阶段验证第一阶段做出的预测，并预测第一阶段未预测的返回从子程序指令的返回地址。 第三阶段执行从子程序返回指令，使得预测得到验证。 最后，第四阶段退出从子程序返回指令，并确保在错误预测的返回地址之后没有指令提取到永久状态。

公开(公告)号：US5574871A

公开(公告)日：1996-11-12

申请号：US177155

申请日：1994-01-04

申请人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani K. Gupta ,  Michael A. Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

发明人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani K. Gupta ,  Michael A. Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30054

摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

公开(公告)号：US06393550B1

公开(公告)日：2002-05-21

申请号：US08532225

申请日：1995-09-19

申请人： Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F930

CPC分类号： G06F9/30167 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： Maximum throughput or “back-to-back” scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.

摘要翻译： 通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。 这两个操作通过多种机制来实现。 用于确定源操作数的可用性以及因此用于调度到可用执行单元的依赖指令的准备状态的一种机制依赖于在源操作数为退休或即时值时在分配期间早期设置源有效位。 这允许保留站的就绪逻辑开始调度发送指令。

公开(公告)号：US5809325A

公开(公告)日：1998-09-15

申请号：US676528

申请日：1996-07-09

申请人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

发明人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/384 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891

摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.

公开(公告)号：US5842036A

公开(公告)日：1998-11-24

申请号：US954444

申请日：1997-10-20

申请人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

发明人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/384 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891

摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.

公开(公告)号：US5555432A

公开(公告)日：1996-09-10

申请号：US293388

申请日：1994-08-19

申请人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

发明人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/384 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891

摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.

摘要翻译： 公开了一种包括执行单元，存储单元和调度器的乱序执行处理器。 存储单元存储等待执行所需资源的可用性的指令。 调度器周期性地确定执行每个指令所需的资源是否可用，如果是，则将该指令分派到执行单元。 执行单元在实际可用的硬件资源之前指示诸如功能单元和写回端口的硬件资源的未来可用性数个时钟周期。 调度器基于硬件资源的未来可用性的指示来确定执行指令所需的资源的可用性，并且分派用于执行的指令。 无序执行处理器还包括在实际完成执行之前确定源指令执行的多个时钟周期的未来完成的装置。 调度器调度执行需要对操作数的这种源指令之一的执行结果的数据相关指令。 一旦源指令的执行结果可用，旁路多路复用器将执行结果旁路到分派的数据相关指令中。 旁路复用器将具有完全组合的操作数的数据相关指令发送到执行单元以供执行。

公开(公告)号：US5553256A

公开(公告)日：1996-09-03

申请号：US464571

申请日：1995-06-05

申请人： Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F9/06

CPC分类号： G06F9/30167 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.

摘要翻译： 通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。 这两个操作通过多种机制来实现。 用于确定源操作数的可用性以及因此用于调度到可用执行单元的依赖指令的准备状态的一种机制依赖于在源操作数为退休或即时值时在分配期间早期设置源有效位。 这允许保留站的就绪逻辑开始调度发送指令。

公开(公告)号：US5768576A

公开(公告)日：1998-06-16

申请号：US739743

申请日：1996-10-29

申请人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

发明人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

IPC分类号： G06F9/38 ,  G06F9/42

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/4426

摘要： A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the instruction stream. The first stage stores a return address in a return register when a Call Subroutine instruction is predicted. The first stage predicts a return to the return address in the return register when a Return From Subroutine instruction is predicted. A second stage decodes each Call Subroutine and Return From Subroutine instruction in order to maintain a Return Stack Buffer that stores a stack of return addresses. Each time the second stage decodes a Call Subroutine instruction, a return address is pushed onto the Return Stack Buffer. Correspondingly, each time the second stage decodes a Return From Subroutine instruction, a return address is popped off of the Return Stack Buffer. The second stage verifies predictions made by the first stage and predicts return addresses for Return From Subroutine instructions that were not predicted by the first stage. A third stage executes Return From Subroutine instructions such that the predictions are verified. Finally, a fourth stage retires Return From Subroutine instructions and ensures that no instructions fetch after a mispredicted return address are committed into permanent state.

摘要翻译： 公开了一种用于解决计算机处理器中的子程序返回指令的方法和装置。 该方法和设备分四个阶段解析子程序指令。 第一阶段预测指令流中的调用子程序指令和子程序返回指令。 当预测一个调用子程序指令时，第一阶段将返回地址存储在一个返回寄存器中。 第一阶段预测当返回从子程序指令被预测时返回寄存器中的返回地址。 第二阶段解码每个调用子程序和从子程序返回指令，以便维护一个存储一堆返回地址的返回栈缓冲区。 每次第二阶段解码一个调用子程序指令时，一个返回地址被推到返回栈缓冲区上。 相应地，每次第二级解码从子程序返回指令时，返回地址从返回堆栈缓冲区中弹出。 第二阶段验证第一阶段做出的预测，并预测第一阶段未预测的返回从子程序指令的返回地址。 第三阶段执行从子程序返回指令，使得预测得到验证。 最后，第四阶段退出从子程序返回指令，并确保在错误预测的返回地址之后没有指令提取到永久状态。

公开(公告)号：US5918046A

公开(公告)日：1999-06-29

申请号：US783073

申请日：1997-01-15

申请人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Subramanian Natarajan ,  Reynold V. D'Sa

发明人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Subramanian Natarajan ,  Reynold V. D'Sa

IPC分类号： G06F9/38 ,  G06F9/40

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/322 ,  G06F9/3861

摘要： A buffer is used to store information about the branch instructions within a pipelined microprocessor that can speculatively execute instructions. When a branch instruction in the microprocessor is decoded, the address of the instruction immediately following the branch instruction (the Next Linear Instruction Pointer or NLIP) and some processor state information is written into a Branch Instruction Pointer Table. The branch instruction then proceeds down the microprocessor pipeline. Eventually, the branch instruction is executed. The resolved branch outcome for the branch instruction is compared with a predicted branch outcome. If the branch prediction was correct, the microprocessor continues execution along the current path. However, if the branch prediction was wrong then the execution unit flushes the front-end microprocessor pipeline and restores the microprocessor state information that was stored in the Branch IP Table. If the branch was mispredicted as not taken, the execution unit instructs an Instruction Fetch Unit to resume execution at a final branch target address. Alternatively, if the branch was mispredicted as taken when the branch should not have been taken, the execution unit instructs the Instruction Fetch Unit to resume execution at the Next Linear Instruction Pointer (NLIP) address stored in the Branch IP Table.

摘要翻译： 缓冲器用于存储可以推测性地执行指令的流水线微处理器内关于分支指令的信息。 当微处理器中的分支指令被解码时，紧跟在分支指令（下一个线性指令指针或NLIP）之后的指令的地址和一些处理器状态信息被写入分支指令指针表。 然后分支指令继续沿着微处理器管线。 最终执行分支指令。 将分支指令的分解结果与预测的分支结果进行比较。 如果分支预测是正确的，则微处理器沿着当前路径继续执行。 然而，如果分支预测错误，则执行单元刷新前端微处理器流水线并恢复存储在分支IP表中的微处理器状态信息。 如果分支被错误预测为未被执行，则执行单元指示指令获取单元在最终分支目标地址处恢复执行。 或者，如果在不支持分支时分支被错误预测，则执行单元指示指令获取单元在存储在分支IP表中的下一个线性指令指针（NLIP）地址处继续执行。