公开(公告)号：US20130275727A1

公开(公告)日：2013-10-17

申请号：US13976580

申请日：2011-12-22

申请人： Seth Abraham ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Zeev Sperber ,  Amit Gradstein

发明人： Seth Abraham ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3455

摘要： A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.

摘要翻译： 方面的方法包括接收指令。 该指令指示整数步长，表示整数偏移，并指示目的地存储位置。 结果存储在目的地存储位置以响应该指令。 结果包括以数字顺序的至少四个整数的序列，其中至少四个整数中的最小的整数与零与整数偏移不同，并且具有与整数步长不同的连续位置中的序列的所有整数。 公开了其它方法，装置，系统和指令。

公开(公告)号：US20110307687A1

公开(公告)日：2011-12-15

申请号：US13219418

申请日：2011-08-26

申请人： ZEEV SPERBER ,  Robert Valentine ,  Benny Eitan ,  Doron Orenstein

发明人： ZEEV SPERBER ,  Robert Valentine ,  Benny Eitan ,  Doron Orenstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3887

摘要： In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand.

摘要翻译： 描述车道内向量随机操作。 在一个实施例中，混洗指令指定每通道控制位，源操作数和目的地操作数的字段，这些操作数具有相应的通道，每个通道被划分为多个数据元素的相应部分。 根据每通道控制位，从源操作数的每个通道的相应部分中选择数据元素的集合。 这些集合的元素被复制到目标操作数的每个通道的相应部分中的指定字段。 混洗指令的另一实施例还指定第二源操作数，所有操作数具有被划分为多个数据元素的相应通道。 根据每通道控制位选择的集合包含来自第一源操作数的每个通道部分的数据元素和来自第二源操作数的每个对应通道部分的数据元素。 将元素复制到目标操作数的每个通道中的指定字段。

公开(公告)号：US20090164763A1

公开(公告)日：2009-06-25

申请号：US11963295

申请日：2007-12-21

申请人： Zeev Sperber ,  Robert Valentine ,  Ehud Cohen ,  Doron Orenstlen ,  Benny Eitan

发明人： Zeev Sperber ,  Robert Valentine ,  Ehud Cohen ,  Doron Orenstlen ,  Benny Eitan

IPC分类号： G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3806 ,  G06F9/3808 ,  G06F9/3834 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/3887

摘要： A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-bit load.

摘要翻译： 提供执行N位或2N位负载的单个微指令。 具有N位负载端口的微处理器在单个周期中执行N位负载或2N位负载，同时使用相同的微指令用于N位和2N位负载。

公开(公告)号：US07162614B2

公开(公告)日：2007-01-09

申请号：US10608121

申请日：2003-06-30

申请人： Zeev Sperber ,  Robert Valentine ,  Yuval Bustan ,  Rafi Marom

发明人： Zeev Sperber ,  Robert Valentine ,  Yuval Bustan ,  Rafi Marom

IPC分类号： G06F9/38

CPC分类号： G06F9/384 ,  G06F9/3836 ,  G06F9/3857

摘要： Two or more pointers, each of which indicates where values of a respective group of bits of a source of a particular micro-operation will be found when the particular micro-operation is executed, may not all point to the same register. Renaming of the source of the particular micro-operation may be enabled by generating one or more new micro-operations that merge the values into a single register. The one or more new micro-operations are inserted into a sequence of micro-operations that includes the particular micro-operation. Once the source of the particular micro-operation has been renamed, subsequent micro-operations in the sequence may be renamed, if appropriate, and executed, without having to wait for the values to be calculated.

摘要翻译： 两个或更多个指针，每个指针指示当执行特定微操作时将发现特定微操作的源的相应组的位置的值，其可能不都指向相同的寄存器。 可以通过生成将值合并到单个寄存器中的一个或多个新的微操作来实现特定微操作的源的重命名。 一个或多个新的微操作被插入到包括特定微操作的微操作的序列中。 一旦特定微操作的源被重新命名，则可以重新命名该序列中的后续微操作，如果适用并被执行，而不必等待该值被计算。

公开(公告)号：US20090249036A1

公开(公告)日：2009-10-01

申请号：US12060239

申请日：2008-03-31

申请人： Lihu Rappoport ,  Robert Valentine ,  Stephan Jourdan ,  Franck Sala ,  Amir Leibovitz ,  Ido Ouziel ,  Ron Gabor

发明人： Lihu Rappoport ,  Robert Valentine ,  Stephan Jourdan ,  Franck Sala ,  Amir Leibovitz ,  Ido Ouziel ,  Ron Gabor

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F1/3203 ,  G06F1/3246 ,  G06F1/3287 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/382 ,  Y02D10/171

摘要： Methods and apparatus for using micro-op caches in processors are disclosed. A tag match for an instruction pointer retrieves a set of micro-op cache line access tuples having matching tags. The set is stored in a match queue. Line access tuples from the match queue are used to access cache lines in a micro-op cache data array to supply a micro-op queue. On a micro-op cache miss, a macroinstruction translation engine (MITE) decodes macroinstructions to supply the micro-op queue. Instruction pointers are stored in a miss queue for fetching macroinstructions from the MITE. The MITE may be disabled to conserve power when the miss queue is empty-likewise for the micro-op cache data array when the match queue is empty. Synchronization flags in the last micro-op from the micro-op cache on a subsequent micro-op cache miss indicate where micro-ops from the MITE merge with micro-ops from the micro-op cache.

摘要翻译： 公开了在处理器中使用微操作高速缓存的方法和装置。 指令指针的标签匹配检索一组具有匹配标签的微操作高速缓存行访问元组。 该集合存储在匹配队列中。 来自匹配队列的线路访问元组用于访问微操作高速缓存数据阵列中的高速缓存行以提供微操作队列。 在微操作缓存未命中时，宏指令转换引擎（MITE）解码宏指令以提供微操作队列。 指令指针存储在从MITE获取宏指令的小队列中。 当缺席队列为空时，MITE可能会被禁用以节省电力，而当匹配队列为空时，也可以为微操作高速缓存数据阵列。 随后微操作高速缓存未命中的微操作高速缓存中的最后一个微操作中的同步标志指示来自MITE的微操作与微操作高速缓存的微操作合并。

公开(公告)号：US10474463B2

公开(公告)日：2019-11-12

申请号：US13997006

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Tal Uliel ,  Jesus Corbal ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Tal Uliel ,  Jesus Corbal ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

摘要： An apparatus and method are described for down-converting from a source operand to a destination operand with masking. For example, a method according to one embodiment includes the following operations: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location.

公开(公告)号：US10095516B2

公开(公告)日：2018-10-09

申请号：US13538523

申请日：2012-06-29

申请人： Shay Gueron ,  Vlad Krasnov ,  Robert Valentine ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

发明人： Shay Gueron ,  Vlad Krasnov ,  Robert Valentine ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

IPC分类号： G06F9/30 ,  G06F7/52 ,  G06F9/38

摘要： An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.

公开(公告)号：US09898283B2

公开(公告)日：2018-02-20

申请号：US13976580

申请日：2011-12-22

申请人： Seth Abraham ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Zeev Sperber ,  Amit Gradstein

发明人： Seth Abraham ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3455

摘要： A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.

公开(公告)号：US09678751B2

公开(公告)日：2017-06-13

申请号：US13977612

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Moustapha Hagog ,  Robert Valentine ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber ,  Boris Ginzburg ,  Ziv Aviv

发明人： Elmoustapha Ould-Ahmed-Vall ,  Moustapha Hagog ,  Robert Valentine ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber ,  Boris Ginzburg ,  Ziv Aviv

IPC分类号： G06F9/30

CPC分类号： G06F9/30036 ,  G06F9/30014 ,  G06F9/30101

摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal partial sum of packed data elements in response to a single vector packed horizontal sum instruction that includes a destination vector register operand, a source vector register operand, and an opcode are described.

公开(公告)号：US09495162B2

公开(公告)日：2016-11-15

申请号：US13996072

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mostafa Hagog ,  Jesus Corbal ,  Tal Uliel ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mostafa Hagog ,  Jesus Corbal ,  Tal Uliel ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30196 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

摘要： An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for a particular data element, then selecting data elements from the destination operand and a second source operand based on index values stored in a first source operand to be copied to data element positions within the destination operand, wherein any one of the data elements from either the destination operand and the second source operand may be copied to any one of the data element positions within the destination operand; if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with respect to that particular data element.

摘要翻译： 描述了用掩模来置换数据元素的装置和方法。 例如，根据一个实施例的方法包括以下操作：从掩模数据结构读取值以确定是否对目的地操作数的每个数据元素实施掩蔽; 如果对特定数据元素没有实现掩蔽，则根据存储在第一源操作数中的索引值从目的地操作数和第二源操作数中选择要复制到目的地操作数内的数据元素位置的第二源操作数，其中， 来自目的地操作数和第二源操作数的数据元素可以被复制到目的地操作数中的任何一个数据元素位置; 如果针对目的地操作数的特定数据元素实现掩蔽，则对该特定数据元素执行指定的屏蔽操作。