公开(公告)号：US20230186998A1

公开(公告)日：2023-06-15

申请号：US17551640

申请日：2021-12-15

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Abhijith Prakash ,  Shubhajit Mukherjee

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/16 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/32 ,  G11C16/3404

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells configured to retain a threshold voltage. The memory cells are connected to one of a plurality of word lines and are arranged in strings comprising a plurality of blocks. A control means is coupled to the plurality of word lines and the strings and is configured to periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells. The control means is also configured to relocate data of the one of the plurality of blocks and cause the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.

公开(公告)号：US20230186993A1

公开(公告)日：2023-06-15

申请号：US18109466

申请日：2023-02-14

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/10

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/10 ,  H10B41/10

Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.

公开(公告)号：US20230154550A1

公开(公告)日：2023-05-18

申请号：US17529722

申请日：2021-11-18

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Abhijith Prakash

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/28 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/3404 ,  G11C16/16 ,  G11C16/28 ,  G11C16/08 ,  G11C16/0433

Abstract: A method of erasing memory cells in a memory device is provided. The method includes grouping a plurality of word lines into a first group, which does not include edge word lines, and a second group, which does include edge word lines. An erase operation is performed on the memory cells of the first and second groups until erase-verify of the memory cells of the first group passes. It is then determined if further erase of the memory cells of the second group is necessary. In response to it being determined that the additional erase operation is necessary, an additional erase operation is performed on at least some of the memory cells of the second group until erase-verify of the memory cells of the second group passes.

公开(公告)号：US20220366990A1

公开(公告)日：2022-11-17

申请号：US17318529

申请日：2021-05-12

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash

IPC: G11C16/30 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

Abstract: Apparatuses and techniques are described for reducing peak current consumption in a memory device when performing a word line voltage refresh operation or a read operation. When a word line voltage refresh operation or read operation is performed for the first time after a memory device powers up, the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps, initiating the ramp up for different groups of word lines in a block at different times, initiating the ramp up for different blocks of word lines at different times, and reducing the number of blocks which are refreshed concurrently. When an additional word line voltage refresh operation or read operation is subsequently performed, the power-saving technique can be omitted.

公开(公告)号：US20220328112A1

公开(公告)日：2022-10-13

申请号：US17229705

申请日：2021-04-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Jiahui Yuan ,  Abhijith Prakash

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/08

Abstract: Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass voltages of the adjacent unselected word lines. If an additional program pulse is applied, the step up in the program pulse can be omitted. The magnitude of the first program level can be adjusted based on factors such as temperature, number of program-erase cycles, selected sub-block position and selected word line position.

公开(公告)号：US11450393B1

公开(公告)日：2022-09-20

申请号：US17195878

申请日：2021-03-09

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04

Abstract: A non-volatile memory apparatus and method of operation are provided. The apparatus includes storage elements connected to a word line. Each of the storage elements is configured to be programmed to a respective target data state. The apparatus also includes a respective bit line associated with each of the storage elements and a control circuit configured to apply a plurality of program pulses to the word line that progressively increase by a program step voltage. The control circuit counts an over programming number of the storage elements having a threshold voltage exceeding an over programming verify level of the respective target data state that is less than a default verify level and based on the program step voltage. The control circuit adjusts a voltage of the respective bit line to one or more adjusted levels in response to the over programming number being greater than a predetermined over programming number.

公开(公告)号：US20220284971A1

公开(公告)日：2022-09-08

申请号：US17192090

申请日：2021-03-04

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A memory apparatus and method of operation are provided. The apparatus includes a plurality of memory cells. Each of the plurality of memory cells is connected to one of a plurality of word lines and is arranged in one of a plurality of blocks. Each of the plurality of memory cells is configured to retain a threshold voltage corresponding to one of a plurality of data states. A control circuit is coupled to the plurality of word lines and is configured to detect at least one use characteristic of the memory apparatus. The control circuit adjusts a verify voltage level by one of a plurality of verify level offsets based on the at least one use characteristic that is detected. The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation.

公开(公告)号：US11043280B1

公开(公告)日：2021-06-22

申请号：US16790306

申请日：2020-02-13

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Jiahui Yuan

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11556

Abstract: Apparatuses and techniques are described for periodically refreshing word line voltages in a group of blocks in a memory device. In one aspect, each group of blocks stores the same number of bits per cell. For example, one group of blocks can be reserved for single level cell (SLC) data and another group of blocks can be reserved for multi-level cell (MLC) data. A common refresh voltage signal can be applied to the blocks in a group, where the voltage signal is optimized based on the number of bits per cell stored by the memory cells of the group. For an SLC block, the refresh voltage signal can decrease a floating voltage of the word lines. For an MLC block, the refresh voltage signal can increase a floating voltage of the word lines.

公开(公告)号：US11037641B1

公开(公告)日：2021-06-15

申请号：US16704817

申请日：2019-12-05

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Vishwanath Basavaegowda Shanthakumar ,  Jiahui Yuan

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/11556

Abstract: Apparatuses and techniques are described for periodically refreshing word line voltages in a memory device. A decision to perform a refresh operation is made based on the temperature and number of program-erase (P-E) cycles. In one approach, the refresh operation is not performed if the number of P-E cycles is below a threshold number and/or the temperature is below a threshold temperature. When the temperature and number of P-E cycles indicate that a refresh operation should be performed, a timer counts an elapsed time until the elapsed time reaches an allowed discharge time. The allowed discharge time can be based on the temperature, number of P-E cycles, and other factors which affect an expected number of fail bits. The allowed discharge time can also change as the temperature changes during the counting of the elapsed time.

公开(公告)号：US20210174886A1

公开(公告)日：2021-06-10

申请号：US16704817

申请日：2019-12-05

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Vishwanath Basavaegowda Shanthakumar ,  Jiahui Yuan

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26

Abstract: Apparatuses and techniques are described for periodically refreshing word line voltages in a memory device. A decision to perform a refresh operation is made based on the temperature and number of program-erase (P-E) cycles. In one approach, the refresh operation is not performed if the number of P-E cycles is below a threshold number and/or the temperature is below a threshold temperature. When the temperature and number of P-E cycles indicate that a refresh operation should be performed, a timer counts an elapsed time until the elapsed time reaches an allowed discharge time. The allowed discharge time can be based on the temperature, number of P-E cycles, and other factors which affect an expected number of fail bits. The allowed discharge time can also change as the temperature changes during the counting of the elapsed time.