公开(公告)号：US11776589B2

公开(公告)日：2023-10-03

申请号：US17731961

申请日：2022-04-28

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/1012 ,  G11C7/1069 ,  G11C7/1087 ,  G11C7/12

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

公开(公告)号：US11735288B1

公开(公告)日：2023-08-22

申请号：US17672904

申请日：2022-02-16

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G11C2029/5004

Abstract: Technology is disclosed herein for loading redundancy information during a memory system power on read (POR). A memory structure has primary regions (e.g., primary columns) and a number of redundant regions (e.g., redundant columns). The status of the regions is stored in isolation latches during the POR. Initially, simultaneously all latches for primary regions are reset to used and all latches for redundant regions are reset to unused. Then, isolation latches for defective primary regions are set to unused while isolation latches for corresponding redundant regions are set to used. There is no need to individually set isolation latches for redundant regions to unused, which saves time during POR. Moreover, whenever the isolation latch for a defective primary region is set from used to unused, in parallel the isolation latch for the replacement redundant column may be set from unused to used, thereby not incurring a time penalty.

公开(公告)号：US20230077517A1

公开(公告)日：2023-03-16

申请号：US17557236

申请日：2021-12-21

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G06F11/10

Abstract: A non-volatile memory combines a hard bit and a soft bit read into a single, efficient soft sense sequence by using two sense per state level to improve read time efficiency. Rather than a standard hard bit read, where two soft bit reads are performed, offset above and below the hard bit read value, the hard bit read is shifted so that it reliable senses one state but less reliably senses the other state and soft bit data is only determined for the less reliably sensed state. This reduces the amount of soft bit data. The efficient soft sense sequence can be used as a default read mode, providing soft bit information for ECC correction without triggering a read error handling flow. Merging the soft bit and hard bit sense into one sequence can avoid extra overhead for read sequence operations.

公开(公告)号：US20210405920A1

公开(公告)日：2021-12-30

申请号：US16912381

申请日：2020-06-25

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Mark Murin ,  Hua-Ling Cynthia Hsu ,  Tomer Eliash ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/32 ,  H01L25/065

Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.

公开(公告)号：US11004535B1

公开(公告)日：2021-05-11

申请号：US16717494

申请日：2019-12-17

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li ,  Aaron Lee

IPC: G11C29/00 ,  G11C29/02 ,  G11C7/10 ,  G11C11/4094 ,  G11C11/408

Abstract: Apparatuses and techniques are described for reliably storing bad column data in a memory device. Units of bad column data and related units of error detection data are stored in non-adjacent groups of memory cells connected to a word line in a ROM block. A unit of bad column data and a related unit of error detection data can be stored in respective groups of memory cells which are relatively far apart from one another along the word line. This helps ensure that a defect in some NAND strings will not affect both the unit of bad column data and a related unit of error detection data. In another aspect, a unit of bad column data and a related unit of error detection data can be stored using different input/output circuits to further increase robustness.

公开(公告)号：US10726940B2

公开(公告)日：2020-07-28

申请号：US16239517

申请日：2019-01-03

Applicant: SanDisk Technologies LLC

Inventor： Zhuojie Li ,  Hua-Ling Cynthia Hsu ,  Yen-Lung Li ,  Min Peng

IPC: G11C29/00 ,  G11C16/10 ,  G06F11/10

Abstract: Apparatuses, systems, and methods are disclosed for skip inconsistency correction. A skip circuit is configured to skip memory units for read operations and write operations of a memory array, based on a record of memory units identified as faulty. A skip inconsistency detection circuit is configured to detect a skip inconsistency in read data from a memory array. A correction circuit is configured to correct a skip inconsistency and output corrected read data.