公开(公告)号：US10922015B2

公开(公告)日：2021-02-16

申请号：US16002534

申请日：2018-06-07

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F3/06 ,  G06F15/78 ,  G06F15/177

Abstract: A processing system includes a processing unit; a non-volatile memory storing configuration data; and a configuration data client including a register, wherein the configuration data client is configured to receive the configuration data and store the configuration data in the register. The processing system further includes a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data, read from the non-volatile memory, to the configuration data client. The hardware configuration circuit may be configured to receive a command, including an access request, from the processing unit and selectively execute the access request.

公开(公告)号：US10855529B2

公开(公告)日：2020-12-01

申请号：US16679796

申请日：2019-11-11

Applicant: STMicroelectronics Application GmbH

Inventor： Roberto Colombo

IPC: H04L12/24 ,  H03K19/1776 ,  H04L29/06 ,  H04L29/08

Abstract: A hardware configuration circuit can sequentially read data packets from a non-volatile memory. For a first data packet, the circuit is configured to store the configuration data and the address included in the data packet in the register, select a target configuration data client circuit as a function of the address included in the first data packet, transmit a first data signal that includes the configuration data included in the first data packet to the target configuration data client circuit, receive a second data signal that includes configuration data stored in the target configuration data client circuit and the address associated with the target configuration data client circuit, and compare the configuration data and address received from the target configuration data client circuit with the configuration data and address stored in the register.

公开(公告)号：US20190007202A1

公开(公告)日：2019-01-03

申请号：US16022110

申请日：2018-06-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Roberto Colombo ,  Guido Marco Bertoni ,  William Orlando ,  Roberta Vittimani

IPC: H04L9/08 ,  H04L9/14 ,  G06F13/36

Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.

公开(公告)号：US20180330127A1

公开(公告)日：2018-11-15

申请号：US15975460

申请日：2018-05-09

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio

IPC: G06F21/83 ,  G06F21/64 ,  G06F9/38 ,  G06F12/02

CPC classification number: G06F21/83 ,  G06F9/3816 ,  G06F9/445 ,  G06F12/02 ,  G06F21/57 ,  G06F21/64 ,  G06F21/74 ,  G06F2212/7209 ,  H04L9/3234 ,  H04L63/0853

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

公开(公告)号：US12253562B2

公开(公告)日：2025-03-18

申请号：US18186624

申请日：2023-03-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Roberto Colombo ,  Vivek Mohan Sharma

IPC: G06F1/24 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/14

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

公开(公告)号：US11762794B2

公开(公告)日：2023-09-19

申请号：US17747800

申请日：2022-05-18

Applicant: STMicroelectronics Application GMBH

Inventor： Rolf Nandlinger ,  Roberto Colombo

IPC: G06F13/28 ,  G06F9/30 ,  G06F9/38 ,  G06F13/42 ,  G06F21/60 ,  G06F21/72

CPC classification number: G06F13/28 ,  G06F9/30105 ,  G06F9/3877 ,  G06F13/4282 ,  G06F21/602 ,  G06F21/72

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

公开(公告)号：US20230170006A1

公开(公告)日：2023-06-01

申请号：US18056803

申请日：2022-11-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N. V. ,  STMicroelectronics Application GMBH

Inventor： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC: G11C7/24 ,  G11C7/10

CPC classification number: G11C7/24 ,  G11C7/1039 ,  G11C7/1069

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

公开(公告)号：US11281514B2

公开(公告)日：2022-03-22

申请号：US16693103

申请日：2019-11-22

Applicant: STMicroelectronics Application GmbH

Inventor： Roberto Colombo

IPC: G06F13/42 ,  G06F11/07 ,  G06F1/10 ,  G06F1/12

Abstract: A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.

公开(公告)号：US11093658B2

公开(公告)日：2021-08-17

申请号：US15975460

申请日：2018-05-09

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio

IPC: G06F21/83 ,  G06F21/64 ,  G06F12/02 ,  G06F9/38 ,  G06F9/445 ,  H04L9/32 ,  G06F21/57 ,  G09C1/00 ,  G06F21/74 ,  H04W12/106 ,  H04L29/06 ,  H04W4/40 ,  H04W12/03 ,  H04W12/40

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

公开(公告)号：US11057194B2

公开(公告)日：2021-07-06

申请号：US16022033

申请日：2018-06-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Roberto Colombo ,  Guido Marco Bertoni ,  William Orlando ,  Roberta Vittimani

IPC: H04L9/08 ,  G06F13/36 ,  H04L9/14 ,  H04L9/32

Abstract: A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.