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    Scan driver
    31.
    发明授权
    Scan driver 有权

    公开(公告)号：US11120745B2

    公开(公告)日：2021-09-14

    申请号：US16734981

    申请日：2020-01-06

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jong Hee Kim

    IPC: G09G3/3266

    Abstract: A scan driver including stages that are connected to scan lines respectively and supply scan signals to the scan lines in response to voltages of 11th and 12th nodes, and a selective drive circuit that is connected to i (i is a natural number of 2 or greater) stages and includes a first node and a second node. Each of the stages includes a first connection transistor that is connected between the first node and the 11th node and a second connection transistor that is connected between the second node and the 12th node. The first connection transistor and the second connection transistor are turned on by a second control signal to electrically connect the first node to the 11th node and the second node to the 12th node, respectively.

    Stage circuit and scan driver using the same
    32.
    发明授权
    Stage circuit and scan driver using the same 有权

    公开(公告)号：US10235955B2

    公开(公告)日：2019-03-19

    申请号：US15160922

    申请日：2016-05-20

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jong Hee Kim ,  Ji Hye Lee ,  Chong Chul Chai

    IPC: G09G3/36 ,  G11C19/18 ,  G11C19/28

    Abstract: A stage circuit includes an output part configured to supply a carry signal to a first output terminal and a scan signal to a second output terminal, in response to a voltage of a first node, a voltage of a second node, and a first clock signal being supplied to a first input terminal, a controller configured to control the voltage of the second node in response to the first clock signal being supplied to the first input terminal, a pull-up part configured to control the voltage of the first node in response to a carry signal of a previous stage being supplied to a second input terminal, and a pull-down part configured to control the voltage of the first node in response to the voltage of the second node and the carry signal of a next stage being supplied to a third input terminal.

    GATE DRIVER AND DISPLAY DEVICE INCLUDING THE SAME
    37.
    发明申请
    GATE DRIVER AND DISPLAY DEVICE INCLUDING THE SAME 审中-公开
    闸门驱动器和显示装置，包括它们

    公开(公告)号：US20160293131A1

    公开(公告)日：2016-10-06

    申请号：US15084022

    申请日：2016-03-29

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Jong Hee Kim ,  Ji Sun Kim ,  Young Wan Seo ,  Jae Keun Lim ,  Chong Chul Chai

    IPC: G09G5/00 ,  H03K17/687

    CPC classification number: G09G5/00 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08

    Abstract: A gate driver includes a plurality of stage circuits to output a clock signal from the outside as gate signals. A jth stage circuit includes an input unit to charge a first node at an initial voltage when a first input signal is input to a first input terminal, a buffer unit to output the clock signal as a gate signal to an output terminal when the initial voltage is supplied to the first node, a holding unit to maintain the first node at a reset power source level when the clock signal is supplied to the holding unit, and an inverter unit to supply the clock signal or the reset power source to the holding unit. The input unit maintains the first node at a second input signal input voltage to a second input terminal when a third input signal is input to a third input terminal.

    Abstract translation: 栅极驱动器包括从外部输出时钟信号作为门信号的多个级电路。 第j级电路包括：输入单元，用于当第一输入信号被输入到第一输入端时以初始电压对第一节点充电，当初始电压输入时，将时钟信号作为门信号输出到输出端; 提供给第一节点的保持单元，当将时钟信号提供给保持单元时，保持单元将第一节点维持在复位电源电平;以及逆变器单元，用于将时钟信号或复位电源提供给保持单元 。 当第三输入信号被输入到第三输入端时，输入单元将第一节点保持在第二输入信号输入电压到第二输入端。

    DISPLAY DEVICE
    38.
    发明申请
    DISPLAY DEVICE 审中-公开
    显示设备

    公开(公告)号：US20160291368A1

    公开(公告)日：2016-10-06

    申请号：US14997817

    申请日：2016-01-18

    Applicant: Samsung Display Co., Ltd.

    Inventor： Ji Sun Kim ,  Jong Hee Kim ,  Young Wan Seo ,  Jae Keun Lim

    IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1343 ,  H01L27/12

    CPC classification number: G02F1/136286 ,  G02F1/1343 ,  H01L27/124 ,  H01L27/1255

    Abstract: Embodiments relate to a display device including: a first base substrate; gate lines disposed on the first base substrate, the gate lines extending in a first direction; parasitic capacitance electrodes coupled to the gate lines; data lines extending in a second direction crossing the first direction; transistors, each coupled to one of the gate lines and coupled to one of the data lines; and pixels sequentially arranged in the first direction, each of the pixels coupled to a corresponding one of the transistors, respectively. Each of the transistors includes a gate electrode, a source electrode, and a drain electrode, and at least two drain electrodes among the drain electrodes of the transistors each overlap a corresponding one of the parasitic capacitance electrodes in different areas as viewed from a plan view.

    Abstract translation: 实施例涉及一种显示装置，包括：第一基底; 设置在第一基底基板上的栅极线，栅极线沿第一方向延伸; 耦合到栅极线的寄生电容电极; 数据线沿与第一方向交叉的第二方向延伸; 晶体管，每个耦合到一条栅极线并耦合到数据线之一; 以及沿第一方向依次布置的像素，每个像素分别耦合到相应的一个晶体管。 每个晶体管包括栅电极，源电极和漏电极，并且晶体管的漏电极中的至少两个漏极电极与从平面图观察的不同区域中的相应的一个寄生电容电极重叠 。

    Display panel
    39.
    发明授权
    Display panel 有权
    显示面板

    公开(公告)号：US09087468B2

    公开(公告)日：2015-07-21

    申请号：US13924221

    申请日：2013-06-21

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Soo-Wan Yoon ,  Yeong-Keun Kwon ,  Ji-Sun Kim ,  Jong Hee Kim ,  Young Wan Seo ,  Jae Keun Lim

    IPC: G09G5/00 ,  G09G3/32 ,  G09G3/36 ,  G11C19/28

    CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G3/3696 ,  G09G5/001 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2320/0214 ,  G11C19/28

    Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

    Abstract translation: 显示装置包括包括栅极线和数据线的显示区域和连接到栅极线的端部的栅极驱动器，栅极驱动器包括集成在被配置为输出栅极电压的衬底上的至少一个级，其中， 该级包括逆变器单元和输出单元，其中输出单元包括第一晶体管和第一电容器。 第一晶体管包括施加有时钟信号的输入端子，连接到节点Q的控制端子以及连接到输出栅极电压的栅极电压输出端子的输出端子。 逆变器输出的逆变器电压低于输出单元输出的栅极电压的低电压。

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