公开(公告)号：US11315649B2

公开(公告)日：2022-04-26

申请号：US16999964

申请日：2020-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Yu ,  Dongkyo Shim

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G06F3/06 ,  G11C16/04 ,  H01L23/00

Abstract: Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.

公开(公告)号：US11132312B2

公开(公告)日：2021-09-28

申请号：US16835922

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Jaeduk Yu

IPC: G11C11/56 ,  G06F13/16 ,  G06F11/07 ,  G01R31/28 ,  G11C7/20

Abstract: To control initialization of a nonvolatile memory device, before assembling a memory system including a first nonvolatile memory device and a second nonvolatile memory device, information data for initialization of the first nonvolatile memory device are stored in the first nonvolatile memory device. After assembling the memory system, the information data are moved from the first nonvolatile memory device to the second nonvolatile memory device. The first nonvolatile memory device is initialized based on the information data stored in the second nonvolatile memory device. An initialization time of the first nonvolatile memory device is reduced efficiently by moving the information data from the first nonvolatile memory device to the second nonvolatile memory device having the rapid speed of the reading operation and using the information data read from the second nonvolatile memory device.

公开(公告)号：US11024363B2

公开(公告)日：2021-06-01

申请号：US16810527

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Bongsoon Lim ,  Jaeduk Yu

IPC: G11C5/02 ,  G11C11/408 ,  G11C11/4094 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04

Abstract: A memory device includes word lines stacked on an upper surface of a substrate, channel structures penetrating through the word lines, and each including channel regions connected to one another in a first direction perpendicular to the upper surface of the substrate, and word-line cuts extending in the first direction and dividing the word lines to blocks. The word lines and the channel structures provide memory cell strings, and each of the memory cell strings include memory cells arranged in the first direction. The memory cells included in at least one of the memory cell strings include a first memory cell and a second memory cell disposed at different positions in the first direction, and the number of bits of data stored in the first memory cell is less than the number of bits of data stored in the second memory cell.

公开(公告)号：US20210098072A1

公开(公告)日：2021-04-01

申请号：US17022967

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/18 ,  G11C29/44 ,  G11C29/12

Abstract: A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US20200381068A1

公开(公告)日：2020-12-03

申请号：US16999964

申请日：2020-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Yu ,  Dongkyo Shim

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G06F3/06

Abstract: Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.