公开(公告)号：US20220376102A1

公开(公告)日：2022-11-24

申请号：US17475700

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu HWANG ,  Jaejoon OH ,  Jongseob KIM

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47

Abstract: A high electron mobility transistor (HEMT) includes an active region, in which a channel is formed, and a field region surrounding the active region. The HEMT may include a channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer; a source and a drain on the barrier layer in the active region; and a gate on the barrier layer. The gate may protrude from the active region to the field region on the barrier layer. The gate may include a first gate and a second gate. The first gate may be in the active region and the second gate may be in the boundary region between the active region and the field region. A work function of the second gate may be different from a work function of the first gate.

公开(公告)号：US20220367698A1

公开(公告)日：2022-11-17

申请号：US17465212

申请日：2021-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu HWANG ,  Jongseob KIM ,  Joonyong KIM ,  Younghwan PARK ,  Junhyuk PARK ,  Jaejoon OH ,  Injun HWANG

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: A semiconductor integrated circuit device includes: a channel layer, a barrier layer; a first p-type semiconductor layer and a second p-type semiconductor layer, spaced apart from each other on the barrier layer; and a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer may partially inactivate a dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.

公开(公告)号：US20220238706A1

公开(公告)日：2022-07-28

申请号：US17719690

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaejoon OH ,  Jongseob KIM

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66

Abstract: Provided are a high electron mobility transistor and a method of manufacturing the high electron mobility transistor. The high electron mobility transistor includes a gate electrode provided on a depletion forming layer. The gate electrode includes a first gate electrode configured to form an ohmic contact with the depletion forming layer, and a second gate electrode configured to form a Schottky contact with the depletion forming layer.

公开(公告)号：US20210313465A1

公开(公告)日：2021-10-07

申请号：US17349327

申请日：2021-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun HWANG ,  Jongseob KIM ,  Joonyong KIM ,  Younghwan PARK ,  Junhyuk PARK ,  Dongchul SHIN ,  Jaejoon OH ,  Soogine CHONG ,  Sunkyu HWANG

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

Abstract: Provided is a field effect transistor (FET) including a gradually varying composition channel. The FET includes: a drain region; a drift region on the drain region; a channel region on the drift region; a source region on the channel region; a gate penetrating the channel region and the source region in a vertical direction; and a gate oxide surrounding the gate. The channel region has a gradually varying composition along the vertical direction such that an intensity of a polarization in the channel region gradually varies.

公开(公告)号：US20210118942A1

公开(公告)日：2021-04-22

申请号：US16885936

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan PARK ,  Jongseob KIM

IPC: H01L27/15

Abstract: A light-emitting device includes a first electrode layer; a second electrode layer; a third electrode layer separated from the first and second electrode layers; a multi-quantum well (MQW) layer between the first electrode layer and the second and third electrode layers; a first material layer between the first electrode layer and the MQW layer and doped with a first conductive type dopant; a second material layer between the second and third electrode layers and the MQW layer and doped with a second conductive type dopant; a gate insulating layer between the third electrode layer and the second material layer; and a current blocking layer configured to at least partially block a flow of a current between the second electrode layer and the MQW layer.