公开(公告)号：US20240113184A1

公开(公告)日：2024-04-04

申请号：US18193859

申请日：2023-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyuk PARK ,  Jaejoon OH ,  Sunkyu HWANG ,  Boram KIM ,  Jongseob KIM ,  Joonyong KIM ,  Injun HWANG

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device may include a barrier layer on a channel layer, a gate electrode on the barrier layer, a gate semiconductor layer between the barrier layer and the gate electrode, and a source and a drain spaced apart from each other on the channel layer. The barrier layer may have a greater energy band gap than the channel layer. The gate semiconductor layer may include a first surface contacting the barrier layer and a second surface contacting the gate electrode, and a sidewall connecting the first surface with the second surface. An area of the second surface of the gate semiconductor layer may be narrower than an area of the first surface. The sidewall of the gate semiconductor layer may include a plurality of surfaces having different slopes.

公开(公告)号：US20220320327A1

公开(公告)日：2022-10-06

申请号：US17398407

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyong KIM ,  Sunkyu HWANG ,  Jongseob KIM ,  Junhyuk PARK

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/20

Abstract: Provided are a power device and a method of manufacturing the same. The power device may include a channel layer; a source and a drain at respective sides of the channel layer; a gate on the channel layer between the source and the drain; a passivation layer covering the source, the drain, and the gate; and a plurality of field plates in the passivation layer. The plurality of field plates may have different thicknesses. The plurality of field plates may have different widths, different pattern shapes, or both different widths and different pattern shapes.

公开(公告)号：US20220013659A1

公开(公告)日：2022-01-13

申请号：US17082478

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun HWANG ,  Jaejoon OH ,  Soogine CHONG ,  Jongseob KIM ,  Joonyong KIM ,  Junhyuk PARK ,  Sunkyu HWANG

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a channel layer comprising a group III-V compound semiconductor; a barrier layer comprising the group III-V compound semiconductor on the channel layer; a gate electrode on the barrier layer; a source electrode over gate electrode; a drain electrode spaced apart from the source electrode; and a metal wiring layer. A same layer of the metal wiring layer includes a gate wiring connected to the gate electrode, a source field plate connected to the source electrode, and a drain field plate connected to the drain electrode.

公开(公告)号：US20240096944A1

公开(公告)日：2024-03-21

申请号：US18133276

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonyong KIM ,  Sunkyu HWANG ,  Boram KIM ,  Jongseob KIM ,  Junhyuk PARK ,  Jaejoon OH ,  Injun HWANG

IPC: H01L29/06 ,  H01L21/3065 ,  H01L23/473 ,  H01L29/66 ,  H10N39/00

CPC classification number: H01L29/0657 ,  H01L21/3065 ,  H01L23/473 ,  H01L29/66462 ,  H10N39/00 ,  H01L29/7786

Abstract: Provided are a power device and a manufacturing method thereof. A power device includes a compound semiconductor layer epitaxially grown on a substrate, a gate formed on the compound semiconductor layer, a source and a drain provided on either side of the gate, a passivation layer provided to cover the source, drain, and gate, and a cooling space region provided to form a cooling path inside the substrate. The cooling space region may be formed to a predetermined depth from the surface of the substrate and include an enlargement region having a width increasing according to a depth from the surface of the substrate. The width of an inlet of the cooling space region is less than a maximum width of the enlargement region, and the passivation layer and the compound semiconductor layer are provided to open the cooling space region.

公开(公告)号：US20220416070A1

公开(公告)日：2022-12-29

申请号：US17537989

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyuk PARK ,  Sunkyu HWANG ,  Jongseob KIM ,  Joonyong KIM ,  Woochul JEON

IPC: H01L29/778 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure provides a high electron mobility transistor including a channel layer; a barrier layer on the channel layer and configured to induce formation of a 2-dimensional electron gas (2DEG) to the channel layer; a p-type semiconductor layer on the barrier layer; a first passivation layer on the barrier layer and including a quaternary material of Al, Ga, O, and N; a gate electrode on the p-type semiconductor layer; and a source electrode and a drain electrode provided on both sides of the barrier layer and separated from the gate electrode.

公开(公告)号：US20210399120A1

公开(公告)日：2021-12-23

申请号：US17098896

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu HWANG ,  Joonyong KIM ,  Jongseob KIM ,  Junhyuk PARK ,  Boram KIM ,  Younghwan PARK ,  Dongchul SHIN ,  Jaejoon OH ,  Soogine CHONG ,  Injun HWANG

IPC: H01L29/778 ,  H01L29/66

Abstract: Provided is a high electron mobility transistor including: a channel layer comprising a 2-dimensional electron gas (2DEG); a barrier layer on the channel layer and comprising first regions and a second region, the first regions configured to induce the 2DEG of a first density in portions of the channel layer and the second region configured to induce the 2DEG of a second density different from the first density in other portions of the channel layer; source and drain electrodes on the barrier layer; a depletion formation layer formed on the barrier layer between the source and drain electrodes to form a depletion region in the 2DEG; and a gate electrode on the barrier layer. The first regions may include a first edge region and a second edge region corresponding to both ends of a surface of the gate electrode facing the channel layer.

公开(公告)号：US20210118814A1

公开(公告)日：2021-04-22

申请号：US16868745

申请日：2020-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan PARK ,  Jongseob KIM ,  Joonyong KIM ,  Junhyuk PARK ,  Dongchul SHIN ,  Jaejoon OH ,  Soogine CHONG ,  Sunkyu HWANG ,  Injun HWANG

IPC: H01L23/00 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/15

Abstract: A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.

公开(公告)号：US20240204092A1

公开(公告)日：2024-06-20

申请号：US18321284

申请日：2023-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyuk PARK ,  Jaejoon OH ,  Sunkyu HWANG ,  Boram KIM ,  Jongseob KIM ,  Joonyong KIM

IPC: H01L29/778 ,  H01L23/31 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/66462

Abstract: A semiconductor device includes a channel layer, a lower barrier layer on the channel layer and including first impurities, an upper barrier layer arranged on the lower barrier layer and including second impurities having a concentration greater than a concentration of the first impurities, a gate electrode on the upper barrier layer, a gate semiconductor layer between the upper barrier layer and the gate electrode, and a source and a drain that are on the channel layer and are spaced apart from each other.

公开(公告)号：US20230343830A1

公开(公告)日：2023-10-26

申请号：US18306341

申请日：2023-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boram KIM ,  Jongseob KIM ,  Woochul JEON ,  Joonyong KIM ,  Junhyuk PARK ,  Jaejoon OH ,  Sunkyu HWANG ,  Injun HWANG

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/207 ,  H01L29/778

CPC classification number: H01L29/157 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/7786

Abstract: Provided are a nitride semiconductor buffer structure and a semiconductor device including the same. The buffer structure may include a plurality of buffer layers between a substrate and an active layer. The active layer may include a nitride semiconductor. The plurality of buffer layers may be stacked on each other on the substrate. Each of the plurality of buffer layers may have a super lattice structure and may include a doped nitride semiconductor. The plurality of buffer layers may have different compositions from each other. Adjacent buffer layers, among the plurality of buffer layers, may have different doping concentrations from each other.

公开(公告)号：US20220310833A1

公开(公告)日：2022-09-29

申请号：US17386729

申请日：2021-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongchul SHIN ,  Boram KIM ,  Younghwan PARK ,  Jongseob KIM ,  Joonyong KIM ,  Junhyuk PARK ,  Jaejoon OH ,  Minchul YU ,  Soogine CHONG ,  Sunkyu HWANG ,  Injun HWANG

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205

Abstract: A high electron mobility transistor (HEMT) includes a channel layer, a plurality of barrier layers, and a p-type semiconductor layer. The barrier layers have an energy band gap greater than that of the channel layer. A gate electrode is arranged on the p-type semiconductor layer. A source electrode and a drain electrode are apart from the p-type semiconductor layer and the gate electrode on the barrier layers. Impurity concentrations of the barrier layers are different from each other in a drift area between the source electrode and the drain electrode.