公开(公告)号：US20240113184A1

公开(公告)日：2024-04-04

申请号：US18193859

申请日：2023-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyuk PARK ,  Jaejoon OH ,  Sunkyu HWANG ,  Boram KIM ,  Jongseob KIM ,  Joonyong KIM ,  Injun HWANG

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device may include a barrier layer on a channel layer, a gate electrode on the barrier layer, a gate semiconductor layer between the barrier layer and the gate electrode, and a source and a drain spaced apart from each other on the channel layer. The barrier layer may have a greater energy band gap than the channel layer. The gate semiconductor layer may include a first surface contacting the barrier layer and a second surface contacting the gate electrode, and a sidewall connecting the first surface with the second surface. An area of the second surface of the gate semiconductor layer may be narrower than an area of the first surface. The sidewall of the gate semiconductor layer may include a plurality of surfaces having different slopes.

公开(公告)号：US20220148948A1

公开(公告)日：2022-05-12

申请号：US17227850

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan PARK ,  Jongseob KIM ,  Jaejoon OH ,  Soogine CHONG ,  Sunkyu HWANG

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/367 ,  H01L29/20

Abstract: Provided are a semiconductor device package and/or a method of fabricating the semiconductor device package. The semiconductor device package may include a semiconductor device including a plurality of electrode pads on an upper surface of the semiconductor device, a lead frame including a plurality of conductive members bonded to the plurality of electrode pads, and a mold between the plurality of conductive members.

公开(公告)号：US20220320327A1

公开(公告)日：2022-10-06

申请号：US17398407

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyong KIM ,  Sunkyu HWANG ,  Jongseob KIM ,  Junhyuk PARK

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/20

Abstract: Provided are a power device and a method of manufacturing the same. The power device may include a channel layer; a source and a drain at respective sides of the channel layer; a gate on the channel layer between the source and the drain; a passivation layer covering the source, the drain, and the gate; and a plurality of field plates in the passivation layer. The plurality of field plates may have different thicknesses. The plurality of field plates may have different widths, different pattern shapes, or both different widths and different pattern shapes.

公开(公告)号：US20220013659A1

公开(公告)日：2022-01-13

申请号：US17082478

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun HWANG ,  Jaejoon OH ,  Soogine CHONG ,  Jongseob KIM ,  Joonyong KIM ,  Junhyuk PARK ,  Sunkyu HWANG

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a channel layer comprising a group III-V compound semiconductor; a barrier layer comprising the group III-V compound semiconductor on the channel layer; a gate electrode on the barrier layer; a source electrode over gate electrode; a drain electrode spaced apart from the source electrode; and a metal wiring layer. A same layer of the metal wiring layer includes a gate wiring connected to the gate electrode, a source field plate connected to the source electrode, and a drain field plate connected to the drain electrode.

公开(公告)号：US20240274689A1

公开(公告)日：2024-08-15

申请号：US18436512

申请日：2024-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun HWANG ,  Jaejoon OH ,  Boram KIM ,  Sunkyu HWANG

IPC: H01L29/47 ,  H01L27/095 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/475 ,  H01L27/095 ,  H01L29/2003 ,  H01L29/7786

Abstract: A HEMT may include a channel layer including a 2DEG as a channel carrier, first and second electrodes separated on the channel layer, a first semiconductor layer on the channel layer between the first and second electrodes and having a greater band gap greater than the channel layer, a gate stack on the first semiconductor layer, and a gate electrode in ohmic contact with the gate stack. The gate stack may include a lower layer contacting the first semiconductor layer, a second semiconductor layer providing a Schottky barrier on the lower layer, and an upper layer on the second semiconductor layer. The upper layer may be doped with a p-type dopant and may have a lower band gap than the second semiconductor layer.

公开(公告)号：US20240096944A1

公开(公告)日：2024-03-21

申请号：US18133276

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonyong KIM ,  Sunkyu HWANG ,  Boram KIM ,  Jongseob KIM ,  Junhyuk PARK ,  Jaejoon OH ,  Injun HWANG

IPC: H01L29/06 ,  H01L21/3065 ,  H01L23/473 ,  H01L29/66 ,  H10N39/00

CPC classification number: H01L29/0657 ,  H01L21/3065 ,  H01L23/473 ,  H01L29/66462 ,  H10N39/00 ,  H01L29/7786

Abstract: Provided are a power device and a manufacturing method thereof. A power device includes a compound semiconductor layer epitaxially grown on a substrate, a gate formed on the compound semiconductor layer, a source and a drain provided on either side of the gate, a passivation layer provided to cover the source, drain, and gate, and a cooling space region provided to form a cooling path inside the substrate. The cooling space region may be formed to a predetermined depth from the surface of the substrate and include an enlargement region having a width increasing according to a depth from the surface of the substrate. The width of an inlet of the cooling space region is less than a maximum width of the enlargement region, and the passivation layer and the compound semiconductor layer are provided to open the cooling space region.

公开(公告)号：US20220416070A1

公开(公告)日：2022-12-29

申请号：US17537989

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyuk PARK ,  Sunkyu HWANG ,  Jongseob KIM ,  Joonyong KIM ,  Woochul JEON

IPC: H01L29/778 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure provides a high electron mobility transistor including a channel layer; a barrier layer on the channel layer and configured to induce formation of a 2-dimensional electron gas (2DEG) to the channel layer; a p-type semiconductor layer on the barrier layer; a first passivation layer on the barrier layer and including a quaternary material of Al, Ga, O, and N; a gate electrode on the p-type semiconductor layer; and a source electrode and a drain electrode provided on both sides of the barrier layer and separated from the gate electrode.

公开(公告)号：US20220148947A1

公开(公告)日：2022-05-12

申请号：US17192439

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan PARK ,  Jongseob KIM ,  Jaejoon OH ,  Soogine CHONG ,  Sunkyu HWANG

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48

Abstract: A semiconductor device package includes a lead frame, a semiconductor device including a first face connected to the lead frame, a second face that faces the first face, a gate pad, a drain pad, and a source pad, the gate pad exposed on the second face of the semiconductor, the drain pad exposed on the second face of the second face, and the source pad exposed on the second face, a gate clip connected to the gate pad, a drain clip connected to the drain pad, a source clip connected to the source pad, the source clip connected to the lead frame, and a molding that seals the lead frame, the semiconductor device, the source clip, the drain clip, and the gate clip.

公开(公告)号：US20210399120A1

公开(公告)日：2021-12-23

申请号：US17098896

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu HWANG ,  Joonyong KIM ,  Jongseob KIM ,  Junhyuk PARK ,  Boram KIM ,  Younghwan PARK ,  Dongchul SHIN ,  Jaejoon OH ,  Soogine CHONG ,  Injun HWANG

IPC: H01L29/778 ,  H01L29/66

Abstract: Provided is a high electron mobility transistor including: a channel layer comprising a 2-dimensional electron gas (2DEG); a barrier layer on the channel layer and comprising first regions and a second region, the first regions configured to induce the 2DEG of a first density in portions of the channel layer and the second region configured to induce the 2DEG of a second density different from the first density in other portions of the channel layer; source and drain electrodes on the barrier layer; a depletion formation layer formed on the barrier layer between the source and drain electrodes to form a depletion region in the 2DEG; and a gate electrode on the barrier layer. The first regions may include a first edge region and a second edge region corresponding to both ends of a surface of the gate electrode facing the channel layer.

公开(公告)号：US20210118814A1

公开(公告)日：2021-04-22

申请号：US16868745

申请日：2020-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan PARK ,  Jongseob KIM ,  Joonyong KIM ,  Junhyuk PARK ,  Dongchul SHIN ,  Jaejoon OH ,  Soogine CHONG ,  Sunkyu HWANG ,  Injun HWANG

IPC: H01L23/00 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/15

Abstract: A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.