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公开(公告)号:US20220231168A1
公开(公告)日:2022-07-21
申请号:US17657761
申请日:2022-04-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyo Jin KIM , Dong Woo KIM , Sang Moon LEE , Seung Hun LEE
IPC: H01L29/78 , H01L21/768 , H01L21/8238 , H01L29/786 , H01L27/092
Abstract: A semiconductor device includes first and second fin-shaped patterns disposed on a substrate and extending in a first direction, first and second channel layers disposed on the first and second fin-shaped patterns, first and second etch stop layers disposed inside the first and second channel layers, first and second gate structures extending in a second direction different from the first direction on the first channel layer with a first recess formed therebetween, third and fourth gate structures extending in the second direction on the second channel layer with a second recess formed therebetween, the first recess having a first width in the first direction and having a first depth in a third direction perpendicular to the first and second directions, the second recess having a second width different from the first width in the first direction, and having a second depth equal to the first depth in the third direction.
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公开(公告)号:US20210408241A1
公开(公告)日:2021-12-30
申请号:US17471244
申请日:2021-09-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seojin JEONG , Jinyeong JOE , Seokhoon KIM , Jeongho YOO , Seung Hun LEE , Sihyung LEE
IPC: H01L29/16 , H01L29/10 , H01L29/04 , H01L29/167 , H01L29/36 , H01L27/092 , H01L29/06 , H01L21/8238 , H01L21/762 , H01L29/66 , H01L29/08
Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.
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公开(公告)号:US20210388501A1
公开(公告)日:2021-12-16
申请号:US17155672
申请日:2021-01-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Young Uk CHOI , Yeon Tae KIM , Tae Soon PARK , Kee Soo PARK , Sung-Gyu PARK , Kwang-Hyun YANG , Seung Hun LEE
IPC: C23C16/52 , C23C16/455 , C23C16/44 , H01L21/203
Abstract: The present disclosure provides a semiconductor deposition monitoring device comprising a supporting table, a chamber, a lamp, an optical sensor, a conduit, a plurality of sensors in the conduit, and a heat exchanger. The supporting table supports a deposition target wafer on which a deposition material is deposited. The chamber comprises an upper dome and a lower dome. The lamp emits light to the chamber. The optical sensor receives the irradiated light and measures the deposition material formed in the chamber. The conduit has an inlet conduit through which air is injected into the chamber and an outlet conduit through which the air is discharged from the chamber. The plurality of sensors sense information of the air. The sensed information may be used to control the heat exchanger.
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公开(公告)号:US20210234050A1
公开(公告)日:2021-07-29
申请号:US17231120
申请日:2021-04-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seung Hun LEE , Dong Woo KIM , Dong Chan SUH , Sun Jung KIM
IPC: H01L29/786 , H01L29/06 , H01L29/423 , H01L21/02 , H01L21/8238 , H01L29/66 , H01L29/775 , B82Y10/00 , H01L29/08 , H01L27/092
Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.
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公开(公告)号:US20210159246A1
公开(公告)日:2021-05-27
申请号:US17144458
申请日:2021-01-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Namkyu Edward CHO , Seok Hoon KIM , Myung Il KANG , Geo Myung SHIN , Seung Hun LEE , Jeong Yun LEE , Min Hee CHOI , Jeong Min CHOI
IPC: H01L27/11582 , H01L29/66 , H01L21/768 , H01L29/78
Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
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公开(公告)号:US20210118880A1
公开(公告)日:2021-04-22
申请号:US16896423
申请日:2020-06-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyojin KIM , Jihye LEE , Sangmoon LEE , Seung Hun LEE
IPC: H01L27/092 , H01L29/161
Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.
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公开(公告)号:US20200075764A1
公开(公告)日:2020-03-05
申请号:US16412796
申请日:2019-05-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sunguk JANG , Sujin JUNG , Jinyeong JOE , Jeongho YOO , Seung Hun LEE , Jongryeol YOO
IPC: H01L29/78 , H01L29/417 , H01L29/66 , H01L29/08 , H01L29/10 , H01L27/088
Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.
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公开(公告)号:US20190288121A1
公开(公告)日:2019-09-19
申请号:US16435263
申请日:2019-06-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seung Hun LEE , Dong Woo KIM , Dong Chan SUH , Sun Jung KIM
IPC: H01L29/786 , H01L21/02 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/775 , H01L21/8238 , B82Y10/00 , H01L27/092
Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.
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公开(公告)号:US20190181225A1
公开(公告)日:2019-06-13
申请号:US16138064
申请日:2018-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Choeun Lee , Seokhoon Kim , Sanggil Lee , Seung Hun LEE , Min-Hee Choi
IPC: H01L29/08 , H01L29/10 , H01L29/165 , H01L29/04 , H01L27/11 , H01L29/78 , H01L29/06 , H01L21/8238 , H01L21/308 , H01L21/02 , H01L29/66
Abstract: Disclosed is a semiconductor device that comprises a substrate including a first active pattern vertically protruding from a top surface of the substrate, and a first source/drain pattern filing a first recess formed on an upper portion of the first active pattern. The first source/drain pattern comprises a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern. The first semiconductor pattern has a first face, a second face, and a first corner edge defined when the first face and the second face meet with each other. The second semiconductor pattern covers the first face and the second face of the first semiconductor pattern and exposes the first corner edge.
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公开(公告)号:US20190067484A1
公开(公告)日:2019-02-28
申请号:US15995414
申请日:2018-06-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seok Hoon KIM , Dong Myoung KIM , Dong Suk SHIN , Seung Hun LEE , Cho Eun LEE , Hyun Jung LEE , Sung Uk JANG , Edward Nam Kyu CHO , Min-Hee CHOI
IPC: H01L29/78 , H01L29/66 , H01L29/423 , H01L21/8234 , H01L21/768 , H01L21/02
Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
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