公开(公告)号：US12289908B2

公开(公告)日：2025-04-29

申请号：US18661171

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seo Jin Jeong ,  Do Hyun Go ,  Seok Hoon Kim ,  Jung Taek Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Min-Hee Choi ,  Ryong Ha

IPC: H10D30/67 ,  H10D62/13

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

公开(公告)号：US11569389B2

公开(公告)日：2023-01-31

申请号：US17470341

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon Seung Yang ,  Eun Hye Choi ,  Seung Mo Kang ,  Yong Seung Kim ,  Jung Taek Kim ,  Min-Hee Choi

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.

公开(公告)号：US10896964B2

公开(公告)日：2021-01-19

申请号：US16252919

申请日：2019-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Kwan Yu ,  Min-Hee Choi

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

公开(公告)号：US10784379B2

公开(公告)日：2020-09-22

申请号：US15995414

申请日：2018-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Hoon Kim ,  Dong Myoung Kim ,  Dong Suk Shin ,  Seung Hun Lee ,  Cho Eun Lee ,  Hyun Jung Lee ,  Sung Uk Jang ,  Edward Nam Kyu Cho ,  Min-Hee Choi

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L27/088 ,  H01L29/08 ,  H01L29/49 ,  H01L27/12

Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

公开(公告)号：US12021131B2

公开(公告)日：2024-06-25

申请号：US17460446

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seo Jin Jeong ,  Do Hyun Go ,  Seok Hoon Kim ,  Jung Taek Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

公开(公告)号：US11862679B2

公开(公告)日：2024-01-02

申请号：US17686700

申请日：2022-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Hee Choi ,  Seokhoon Kim ,  Choeun Lee ,  Edward Namkyu Cho ,  Seung Hun Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H10B12/00 ,  H01L29/08 ,  H01L29/417 ,  H10B10/00

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/785 ,  H10B10/12 ,  H10B12/36

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern.

公开(公告)号：US11942551B2

公开(公告)日：2024-03-26

申请号：US17519967

申请日：2021-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

公开(公告)号：US11302779B2

公开(公告)日：2022-04-12

申请号：US16452668

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Hee Choi ,  Seokhoon Kim ,  Choeun Lee ,  Edward Namkyu Cho ,  Seung Hun Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/08 ,  H01L27/11 ,  H01L29/417

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern.

公开(公告)号：US11133421B2

公开(公告)日：2021-09-28

申请号：US16808857

申请日：2020-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon Seung Yang ,  Eun Hye Choi ,  Seung Mo Kang ,  Yong Seung Kim ,  Jung Taek Kim ,  Min-Hee Choi

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423

Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.

公开(公告)号：US10297601B2

公开(公告)日：2019-05-21

申请号：US15351739

申请日：2016-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Myung-Gil Kang ,  Kang-Hun Moon ,  Cho-Eun Lee ,  Su-Jin Jung ,  Min-Hee Choi ,  Yang Xu ,  Dong-Suk Shin ,  Kwan-Heum Lee ,  Hoi-Sung Chung

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/45 ,  H01L23/485 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.