公开(公告)号：US20230238283A1

公开(公告)日：2023-07-27

申请号：US18118505

申请日：2023-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun LEE ,  Jeong Yun LEE ,  Seung Ju PARK ,  Geum Jung SEONG ,  Young Mook OH ,  Seung Soo HONG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42364 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/6656

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US20200328207A1

公开(公告)日：2020-10-15

申请号：US16739357

申请日：2020-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Soo HONG ,  Jeong Yun LEE ,  Geum Jung SEONG ,  Jin Won LEE ,  Hyun Ho JUNG

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/11

Abstract: A semiconductor device including a plurality of active regions extending in a first direction on a substrate; a device isolation layer between the plurality of active regions such that upper portions of the plurality of active regions protrude from the device isolation layer; a first gate electrode and a second gate electrode extending in a second direction crossing the first direction and intersecting the plurality of active regions, respectively, on the substrate, the first gate electrode being spaced apart from the second gate electrode in the second direction; a first gate separation layer between the first gate electrode and the second gate electrode; and a second gate separation layer under the first gate separation layer and between the first gate electrode and the second gate electrode, the second gate separation layer extending into the device isolation layer in a third direction crossing the first direction and the second direction.

公开(公告)号：US20230207628A1

公开(公告)日：2023-06-29

申请号：US18115913

申请日：2023-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namkyu Edward CHO ,  Seung Soo HONG ,  Geum Jung SEONG ,  Seung Hun LEE ,  Jeong Yun LEE

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/306 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H10B10/00

CPC classification number: H01L29/0847 ,  H01L21/02576 ,  H01L29/0649 ,  H01L27/0207 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/30604 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/165 ,  H01L29/7848 ,  H01L21/02579 ,  H01L27/0924 ,  H01L29/0869 ,  H10B10/12

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

公开(公告)号：US20210280469A1

公开(公告)日：2021-09-09

申请号：US17328348

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun LEE ,  Jeong Yun LEE ,  Seung Ju PARK ,  Geum Jung SEONG ,  Young Mook OH ,  Seung Soo HONG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US20210159246A1

公开(公告)日：2021-05-27

申请号：US17144458

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu Edward CHO ,  Seok Hoon KIM ,  Myung Il KANG ,  Geo Myung SHIN ,  Seung Hun LEE ,  Jeong Yun LEE ,  Min Hee CHOI ,  Jeong Min CHOI

IPC: H01L27/11582 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

公开(公告)号：US20220059532A1

公开(公告)日：2022-02-24

申请号：US17521011

申请日：2021-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Soo HONG ,  Jeong Yun LEE ,  Geum Jung SEONG ,  Jin Won LEE ,  Hyun Ho JUNG

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/66

Abstract: A semiconductor device including a plurality of active regions extending in a first direction on a substrate; a device isolation layer between the plurality of active regions such that upper portions of the plurality of active regions protrude from the device isolation layer; a first gate electrode and a second gate electrode extending in a second direction crossing the first direction and intersecting the plurality of active regions, respectively, on the substrate, the first gate electrode being spaced apart from the second gate electrode in the second direction; a first gate separation layer between the first gate electrode and the second gate electrode; and a second gate separation layer under the first gate separation layer and between the first gate electrode and the second gate electrode, the second gate separation layer extending into the device isolation layer in a third direction crossing the first direction and the second direction.

公开(公告)号：US20200027895A1

公开(公告)日：2020-01-23

申请号：US16272265

申请日：2019-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu Edward CHO ,  Seok Hoon KIM ,  Myung II KANG ,  Geo Myung SHIN ,  Seung Hun LEE ,  Jeong Yun LEE ,  Min Hee CHOI ,  Jeong Min CHOI

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

公开(公告)号：US20190295889A1

公开(公告)日：2019-09-26

申请号：US16176943

申请日：2018-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hee BAI ,  Sung Woo KANG ,  Kee Sang KWON ,  Dong Seok LEE ,  Sang Hyun LEE ,  Jeong Yun LEE ,  Yong-Ho JEON

IPC: H01L21/768 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device with improved product reliability and a method of fabricating the semiconductor are provided. The semiconductor device includes a substrate, a gate electrode on the substrate, a first spacer on a sidewall of the gate electrode, a conductive contact on a sidewall of the first spacer to protrude beyond a top surface of the gate electrode, a trench defined by the top surface of the gate electrode, a top surface of the first spacer, and sidewalls of the contact, an etching stop layer extending along at least parts of sidewalls of the trench and a bottom surface of the trench, and a capping pattern on the etching stop layer to fill the trench, wherein the capping pattern includes silicon oxide or a low-k material having a lower permittivity than silicon oxide.

公开(公告)号：US20190074211A1

公开(公告)日：2019-03-07

申请号：US15962059

申请日：2018-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Seok MIN ,  Dong Kwon KIM ,  Cheol KIM ,  Young Mook OH ,  Jeong Yun LEE ,  Hyun Ho JUNG

IPC: H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having an active pattern extending in a first direction, a first gate structure and a second gate structure extending in a second direction, intersecting the first direction, to traverse the active pattern, the first gate structure and the second gate structure isolated from each other while facing each other in the second direction, a gate isolation pattern disposed between the first gate structure and the second gate structure, the gate isolation pattern having a void, and a filling insulating portion positioned lower than upper surfaces of the first gate structure and the second gate structure within the gate isolation pattern, the filling insulating portion being connected to at least an upper end of the void.

公开(公告)号：US20170200738A1

公开(公告)日：2017-07-13

申请号：US15403307

申请日：2017-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Soon KIM ,  Hyun Ji KIM ,  Jeong Yun LEE ,  Gi Gwan PARK ,  Sang Duk PARK ,  Young Mook OH ,  Yong Seok LEE

IPC: H01L27/12 ,  H01L29/423 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/7853

Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.