公开(公告)号：US20200089642A1

公开(公告)日：2020-03-19

申请号：US16692997

申请日：2019-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Fred Worley ,  Son Pham

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

Abstract: A system includes a fabric switch including a motherboard, a baseboard management controller (BMC), a network switch configured to transport network signals, and a PCIe switch configured to transport PCIe signals; a midplane; and a plurality of device ports. Each of the plurality of device ports is configured to connect a storage device to the motherboard of the fabric switch over the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable in multiple modes based a protocol established over a fabric connection between the system and the storage device.

公开(公告)号：US10592463B2

公开(公告)日：2020-03-17

申请号：US16124182

申请日：2018-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas P. Kachare ,  Stephen Fischer ,  Fred Worley ,  Sompong Paul Olarig

IPC: G06F13/42 ,  G06F13/16 ,  G06F9/445 ,  G06F13/40

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream endpoint enables communication with the processor; two downstream root ports enable communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include two endpoints of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

公开(公告)号：US20200004719A1

公开(公告)日：2020-01-02

申请号：US16565358

申请日：2019-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig

IPC: G06F13/42 ,  G06F13/16

Abstract: An adaptive interface high availability storage device. In some embodiments, the adaptive interface high availability storage device includes: a rear storage interface connector; a rear multiplexer, connected to the rear storage interface connector; an adaptable circuit connected to the rear multiplexer; a front multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the front multiplexer. The adaptive interface high availability storage device may be configured to operate in a single-port state or in a dual-port state. The adaptive interface high availability storage device may be configured: in the single-port state, to present a single-port host side storage interface according to a first storage protocol at the rear storage interface connector, and in the dual-port state, to present a dual-port host side storage interface according to the first storage protocol at the rear storage interface connector.

公开(公告)号：US10481834B2

公开(公告)日：2019-11-19

申请号：US15944594

申请日：2018-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Vikas K. Sinha ,  Fred Worley ,  Ramdas P. Kachare ,  Stephen G. Fischer

IPC: G06F3/06 ,  G06F12/0868 ,  G06F13/42 ,  G06F12/0806

Abstract: A system and method for providing erasure code data protection for an array of solid state drives. The solid state drives are connected to an Ethernet switch which includes a RAID control circuit, or a state machine, to process read or write commands that may be received from a remote host. The RAID control circuit, if present, uses a low-latency cache to execute write commands, and the state machine, if present, uses a local central processing unit, which in turn uses a memory as a low-latency cache, to similar effect.

公开(公告)号：US20190286352A1

公开(公告)日：2019-09-19

申请号：US16431539

申请日：2019-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig

IPC: G06F3/06 ,  G06F13/42

Abstract: A memory device is configured to communicate with one or more external devices, the memory device including a configurable bit or a mode select pin for determining which one of two or more different communication protocols that the memory device uses to communicate with the one or more external devices, wherein the two or more different communications protocols include at least a Controller Area Network (CAN) protocol and a System Management Bus (SMBus) protocol.

公开(公告)号：US20190278586A1

公开(公告)日：2019-09-12

申请号：US16127061

申请日：2018-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Ramdas P. Kachare ,  Son Truong Pham ,  Fred Worley

IPC: G06F8/654

Abstract: A system and method for updating storage system includes a solid state disk (SSD) attached to a FPGA. The solid state disk is configured to receive a firmware image and a firmware upgrade module operating on the FPGA is configured to identify the presence of the firmware image on the SSD. The firmware upgrade module is further configured to store the firmware image in a buffer on the FPGA and write the firmware image.

公开(公告)号：US20190272215A1

公开(公告)日：2019-09-05

申请号：US16049492

申请日：2018-07-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Fred Worley ,  Oscar P. Pinto ,  Jason Martineau

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G06F13/16 ,  G06F13/42

Abstract: A system and method for supporting data protection across field programmable gate array (FPGA) solid state drives (SSDs) includes a storage system having a first group of solid state drives connected to a FPGA. The FPGA includes a first data protection controller configured to manage input/output requests to and from the first group of solid state disks according to a data protection configuration, generate parity bits according to the data protection configuration, and store the parity bits on at least parity solid state drive from the first group of solid state drives.

公开(公告)号：US20190196909A1

公开(公告)日：2019-06-27

申请号：US16289257

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  David Schwaderer ,  Ramdas P. Kachare

IPC: G06F11/10 ,  G06F11/20 ,  G06F11/08

CPC classification number: G06F11/1084 ,  G06F11/085 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/108 ,  G06F11/1088 ,  G06F11/1092 ,  G06F11/1096 ,  G06F11/1469 ,  G06F11/201 ,  G06F11/2012 ,  G06F11/2087 ,  G06F2201/84

Abstract: A system and method for providing erasure code protection across multiple storage devices. A data switch in a storage system connects a plurality of storage devices to a remote host. Each storage device is also connected to a controller, e.g., a baseboard management controller. During normal operation, read and write commands from the remote host are sent to respective storage devices through the data switch. When a write command is executed, the storage device executing the command sends a copy of the data to the controller, which generates and stores erasure codes, e.g., on a storage device that is dedicated to the storage of erasure codes, and invisible to the remote host. When a device fails or is removed, the controller reconfigures the data switch to redirect all traffic addressed to the failed or absent storage device to the controller, and the controller responds to host commands in its stead.

公开(公告)号：US10311008B2

公开(公告)日：2019-06-04

申请号：US15279424

申请日：2016-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Fred Worley ,  Sompong Paul Olarig ,  Harry Rogers ,  Jason Martineau

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F3/06 ,  H04L29/08 ,  H04L12/46 ,  H05K7/14

Abstract: Embodiments include a storage device, comprising: a chassis; non-volatile storage media disposed on the chassis; a network interface connector integrated with the chassis, wherein the network interface connector integrated with the chassis is structured to be directly inserted into a network switch; and control logic disposed on the chassis and configured to enable access to the non-volatile storage media through the network interface connector.

公开(公告)号：US20180359318A1

公开(公告)日：2018-12-13

申请号：US15678051

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harry Rogers ,  Sompong Paul Olarig ,  Ramdas P. Kachare

IPC: H04L29/08 ,  H04L29/12 ,  G06T1/20 ,  G06F12/02

CPC classification number: H04L67/1097 ,  G06F12/0246 ,  G06F2212/7201 ,  G06T1/20 ,  H04L61/2596

Abstract: A method of transferring data to an end user via a content distribution network using an nonvolatile memory express over fabrics (NVMe-oF) device, the method including receiving a read request at the NVMe-oF device, translating a logical address corresponding to the data to a physical address, fetching the data from a flash storage of the NVMe-oF device, processing the data with a GPU that is either embedded in the NVMe-oF device, or on a same chassis as the NVMe-oF device, and transferring the data.