公开(公告)号：US20060120142A1

公开(公告)日：2006-06-08

申请号：US11266408

申请日：2005-11-04

申请人： Yoshinobu Yamagami

发明人： Yoshinobu Yamagami

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C11/413

摘要： There provided a semiconductor memory device which ensures writing to all memory cells regardless of fluctuations in properties of the memory cells caused by manufacturing error or the like and can reduce write operation time and power consumption. Write operations for a memory cell 1 and a dummy memory cell 1a are controlled based on a write amplifier control signal WAE. Write operation end timing is determined based on a write completion signal WRST which indicates a storage state of the dummy memory cell 1a. The dummy memory cell 1a and peripheral circuitry are designed so that write time required for the dummy memory cell 1a is more than or equal to a maximum of write time required for the memory cells 1.

摘要翻译： 提供了一种半导体存储器件，其保证对所有存储器单元的写入，而不管由制造误差等引起的存储器单元的性质的波动，并且可以减少写入操作时间和功耗。 基于写放大器控制信号WAE来控制存储单元1和虚设存储单元1a的写操作。 基于指示虚拟存储单元1a的存储状态的写入完成信号WRST来确定写入操作结束定时。 伪存储单元1a和外围电路被设计成使得空存储单元1a所需的写入时间大于或等于存储单元1所需的写入时间的最大值。

公开(公告)号：US06999367B2

公开(公告)日：2006-02-14

申请号：US10917308

申请日：2004-08-13

申请人： Yoshinobu Yamagami

发明人： Yoshinobu Yamagami

IPC分类号： G11C7/02 ,  G11C11/40

CPC分类号： G11C11/419

摘要： A semiconductor memory device includes word lines, bit line pairs, memory cells 1, bit line precharge circuits 2, and write amplifiers 3, as well as a dummy word line, a dummy bit line pair, dummy memory cells 1a, 1b, and 1c, and a memory cell storing node detection circuit 6. Through the action of the dummy memory cells 1b and 1c, it is ensured that the write timing for the dummy memory cell 1a is substantially identical to the write timing for the memory cells 1. Based on changes in the states of storing nodes S1 and S2 included in the dummy memory cell 1a, the memory cell storing node detection circuit 6 generates a write completion signal WRST. As a result, a semiconductor memory device having an optimized write timing and low power consumption is provided.

摘要翻译： 半导体存储器件包括字线，位线对，存储单元1，位线预充电电路2和写放大器3，以及虚拟字线，虚拟位线对，虚拟存储器单元1a，1b， 和1c，以及存储单元存储节点检测电路6。 通过虚拟存储器单元1b和1c的动作，确保虚拟存储单元1a的写入定时基本上与存储单元1的写入定时相同。 基于存储在虚拟存储单元1a中的存储节点S 1和S 2的状态的变化，存储单元存储节点检测电路6产生写入完成信号WRST。 结果，提供了具有优化的写入定时和低功耗的半导体存储器件。

公开(公告)号：US20060028896A1

公开(公告)日：2006-02-09

申请号：US11193379

申请日：2005-08-01

申请人： Yoshinobu Yamagami

发明人： Yoshinobu Yamagami

IPC分类号： G11C5/14 ,  G11C7/06

CPC分类号： G11C11/417 ,  G11C2207/2227

摘要： When a memory cell is inactive, a memory cell power supply voltage control circuit decreases the power supply voltage supplied to the memory cell down to a memory cell holding voltage, thereby reducing the leak current flowing in the memory cell. By reducing the leak current, it is possible to reduce the power consumption of a semiconductor memory device and to increase the operating speed thereof. Moreover, the threshold voltage of transistors in the memory cell is kept low, thereby improving the operating characteristics of the semiconductor memory device at low power supply voltages.

摘要翻译： 当存储器单元不活动时，存储单元电源电压控制电路将提供给存储单元的电源电压降低到存储单元保持电压，从而减少在存储单元中流动的漏电流。 通过减小泄漏电流，可以降低半导体存储器件的功耗并提高其工作速度。 此外，存储单元中的晶体管的阈值电压保持为低，从而在低电源电压下改善半导体存储器件的工作特性。

公开(公告)号：US06982912B2

公开(公告)日：2006-01-03

申请号：US10833922

申请日：2004-04-28

申请人： Yoshinobu Yamagami

发明人： Yoshinobu Yamagami

IPC分类号： G11C29/00

CPC分类号： G11C29/83

摘要： The semiconductor memory device comprises a plurality of word lines including one or more redundant word lines; a plurality of pairs of bit lines; a plurality of memory cells connected to the above-mentioned plurality of word lines and the above-mentioned plurality of pairs of bit lines; a plurality of word-line drivers, each of which is connected to respective one ends of the above-mentioned plurality of word lines and controlled by a plurality of word-line control signals; and a plurality of first word-line control circuits respectively located at the other ends of the above-mentioned plurality of word lines, each of the above-mentioned plurality of first word-line control circuits receiving a signal level of a corresponding one of the above-mentioned plurality of word lines.

摘要翻译： 半导体存储器件包括多个字线，包括一个或多个冗余字线; 多对位线; 连接到上述多个字线和上述多对位线的多个存储单元; 多个字线驱动器，其各自连接到上述多个字线的相应一端并被多个字线控制信号控制; 以及分别位于上述多个字线的另一端的多个第一字线控制电路，上述多个第一字线控制电路中的每一个接收相应的一个字线的信号电平 上述多个字线。

公开(公告)号：US08072823B2

公开(公告)日：2011-12-06

申请号：US12910254

申请日：2010-10-22

申请人： Tomoyuki Aihara ,  Masanori Shirahama ,  Yoshinobu Yamagami ,  Marefusa Kurumada ,  Toshikazu Suzuki

发明人： Tomoyuki Aihara ,  Masanori Shirahama ,  Yoshinobu Yamagami ,  Marefusa Kurumada ,  Toshikazu Suzuki

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/413 ,  G11C2207/002 ,  H01L27/0207 ,  H01L27/1104

摘要： A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced.

摘要翻译： 半导体存储器件包括设置在字线和位线的交叉点处的存储单元，连接到位线的预充电电路，根据写控制信号控制的列选择电路，以及设置为 写电路。 钳位电路包括被配置为将选定位线的电位控制为第一电位（例如，0V）的晶体管，以及被配置为将所选位线的电位控制为第二电位的可变电容（例如，负 电位）低于第一电位。 当电源电压增加时，可变电容器的电容减小，从而第一电位降低到第二电位的量减少。

公开(公告)号：US07701783B2

公开(公告)日：2010-04-20

申请号：US12209748

申请日：2008-09-12

申请人： Yoshinobu Yamagami

发明人： Yoshinobu Yamagami

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C11/419

摘要： A semiconductor storage device has memory cells provided at intersections of word lines and bit lines, a precharge circuit connected to the bit lines, and a write circuit. The write circuit includes a column selection circuit controlled by a write control signal, a transistor for controlling a potential of a selected bit line so that the potential of the selected bit line is a first potential (e.g., 0 V), a capacitance element for controlling the potential of the selected bit line so that the potential of the selected bit line is a second potential (e.g., a negative potential) that is lower than the first potential, and a clamp circuit for clamping the second potential when a power supply voltage becomes high.

摘要翻译： 半导体存储装置具有设置在字线和位线的交点处的存储单元，连接到位线的预充电电路和写入电路。 写入电路包括由写入控制信号控制的列选择电路，用于控制所选位线的电位使得所选位线的电位为第一电位（例如，0V）的晶体管，用于 控制所选位线的电位，使得所选位线的电位为低于第一电位的第二电位（例如，负电位）;以及钳位电路，用于在电源电压 变高

公开(公告)号：US07643372B2

公开(公告)日：2010-01-05

申请号：US12100312

申请日：2008-04-09

申请人： Yoshinobu Yamagami

发明人： Yoshinobu Yamagami

IPC分类号： G11C8/08

CPC分类号： G11C8/08 ,  G11C11/412 ,  G11C11/413 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/48 ,  G11C2029/5002 ,  G11C2029/5004 ,  G11C2029/5006

摘要： A semiconductor integrated circuit includes a plurality of memory cells arranged in a matrix, a plurality of word lines corresponding to respective rows of the plurality of memory cells, a plurality of word line drivers for driving the plurality of word lines, respectively, and a plurality of pull-down circuits connected to the plurality of word lines, respectively, for causing voltages of the respective connected word lines to be lower than or equal to a power supply voltage when the respective word lines are in an active state. The word line drivers each have a transistor for causing the corresponding word line to go into the active state. The pull-down circuits each have a pull-down transistor for pulling down the corresponding word line, the pull-down transistor being a transistor having the same conductivity type as that of the transistor included the word line driver for driving the corresponding word line.

摘要翻译： 半导体集成电路包括以矩阵形式排列的多个存储单元，与多个存储单元的各行相对应的多个字线，分别驱动多个字线的多个字线驱动器和多个 分别连接到多个字线的下拉电路，用于当各个字线处于活动状态时使各个连接字线的电压低于或等于电源电压。 字线驱动器各自具有用于使相应的字线进入活动状态的晶体管。 下拉电路各自具有用于拉低对应字线的下拉晶体管，下拉晶体管是具有与包括用于驱动相应字线的字线驱动器的晶体管相同的导电类型的晶体管。

公开(公告)号：US07433257B2

公开(公告)日：2008-10-07

申请号：US11193379

申请日：2005-08-01

申请人： Yoshinobu Yamagami

发明人： Yoshinobu Yamagami

IPC分类号： G11C5/14 ,  G11C11/413

CPC分类号： G11C11/417 ,  G11C2207/2227

摘要： When a memory cell is inactive, a memory cell power supply voltage control circuit decreases the power supply voltage supplied to the memory cell down to a memory cell holding voltage, thereby reducing the leak current flowing in the memory cell. By reducing the leak current, it is possible to reduce the power consumption of a semiconductor memory device and to increase the operating speed thereof. Moreover, the threshold voltage of transistors in the memory cell is kept low, thereby improving the operating characteristics of the semiconductor memory device at low power supply voltages.

摘要翻译： 当存储器单元不活动时，存储单元电源电压控制电路将提供给存储单元的电源电压降低到存储单元保持电压，从而减少在存储单元中流动的漏电流。 通过减小泄漏电流，可以降低半导体存储器件的功耗并提高其工作速度。 此外，存储单元中的晶体管的阈值电压保持为低，从而在低电源电压下改善半导体存储器件的工作特性。

公开(公告)号：US06937532B2

公开(公告)日：2005-08-30

申请号：US10628168

申请日：2003-07-28

申请人： Ichiro Hatanaka ,  Akinori Shibayama ,  Yoshinobu Yamagami

发明人： Ichiro Hatanaka ,  Akinori Shibayama ,  Yoshinobu Yamagami

IPC分类号： G11C11/413 ,  G11C5/02 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L27/11 ,  G11C7/00

CPC分类号： G11C5/025 ,  G11C29/78

摘要： A semiconductor memory includes a memory cell array, a redundancy repair signal generator, and a row decoder. The memory cell array includes a plurality of memory cell rows and at least one redundant memory cell row. The redundancy repair signal generator generates a redundancy repair signal that indicates an address of a defective memory cell row. The row decoder receives a row address signal that indicates a memory cell row including a memory cell to be accessed and selects the redundant memory cell row in accordance with the redundancy repair signal generated by the redundancy repair signal generator. The redundancy repair signal generator is located opposite to the row decoder with the memory cell array placed therebetween. This configuration can achieve a reduction in free space and thus a reduction in area loss.

摘要翻译： 半导体存储器包括存储单元阵列，冗余修复信号发生器和行解码器。 存储单元阵列包括多个存储单元行和至少一个冗余存储单元行。 冗余修复信号发生器产生指示有缺陷的存储器单元行的地址的冗余修复信号。 行解码器接收指示包括要访问的存储单元的存储单元行的行地址信号，并根据由冗余修复信号发生器产生的冗余修复信号选择冗余存储单元行。 冗余修复信号发生器位于与行解码器相对的位置，存储单元阵列位于它们之间。 这种构造可以实现自由空间的减小，从而减少面积损耗。

公开(公告)号：US06762971B2

公开(公告)日：2004-07-13

申请号：US10430050

申请日：2003-05-06

申请人： Yoshinobu Yamagami

发明人： Yoshinobu Yamagami

IPC分类号： G11C800

CPC分类号： G11C29/70 ,  G11C8/08 ,  G11C29/832

摘要： A semiconductor memory device comprises plural word lines including one or more redundant word lines, plural pairs of bit lines, plural memory cells connected to the plural word lines and the plural pairs of bit lines, plural word-line drivers which are connected to one ends of the plural word lines and controlled by plural word-line control signals respectively, and plural word-line control elements which are connected to other ends of the plural word lines and controlled by a control signal activated at the precharge of the bit lines.

摘要翻译： 半导体存储器件包括多个字线，包括一个或多个冗余字线，多对位线，连接到多个字线和多对位线的多个存储单元，连接到一端的多个字线驱动器 分别由多个字线控制信号控制，并且多个字线控制元件连接到多个字线的另一端并由在位线的预充电激活的控制信号控制。