公开(公告)号：US06725325B2

公开(公告)日：2004-04-20

申请号：US10005361

申请日：2001-12-07

申请人： Masahiko Nishiyama ,  Kinya Mitsumoto ,  Takeshi Agari

发明人： Masahiko Nishiyama ,  Kinya Mitsumoto ,  Takeshi Agari

IPC分类号： G06F1300

CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22

摘要： A semiconductor memory device having a double data rate (DDR) mode includes a first comparison logic circuit comparing the lower bits of a specified memory address for a reading operation with the lower bits of a specified memory address for a preceding writing operation, a second comparison logic circuit detecting if bits other than the lower bits match, and a third comparison logic circuit detecting that, when a match is obtained from the second comparison logic circuit, the lower bits of the specified memory address or a secondary memory address such as a burst address for the reading operation match the lower bits of the specified memory address or secondary memory address for the preceding writing operation. The device may have a late write function and a register may be provided to latch single data rate (SDR)/DDR mode information.

摘要翻译： 具有双数据速率（DDR）模式的半导体存储器件包括第一比较逻辑电路，用于将用于读取操作的指定存储器地址的较低位与用于先前写入操作的指​​定存储器地址的较低位进行比较，第二比较 逻辑电路检测低位以外的比特是否匹配;以及第三比较逻辑电路，检测当从第二比较逻辑电路获得匹配时，指定存储器地址的较低位或诸如脉冲串的次要存储器地址 读取操作的地址与上一次写入操作的指​​定存储器地址或辅助存储器地址的低位相匹配。 该装置可能具有迟写功能，并且可以提供寄存器来锁存单数据速率（SDR）/ DDR模式信息。

公开(公告)号：US5050127A

公开(公告)日：1991-09-17

申请号：US423947

申请日：1989-10-19

申请人： Kinya Mitsumoto ,  Shinji Nakazato ,  Yoshiaki Yazawa ,  Masanori Odaka ,  Hideaki Uchida ,  Nobuaki Miyakawa

发明人： Kinya Mitsumoto ,  Shinji Nakazato ,  Yoshiaki Yazawa ,  Masanori Odaka ,  Hideaki Uchida ,  Nobuaki Miyakawa

IPC分类号： G11C11/417 ,  G11C7/10

CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

摘要： A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

公开(公告)号：US4829479A

公开(公告)日：1989-05-09

申请号：US108623

申请日：1987-10-15

申请人： Kinya Mitsumoto ,  Shinji Nakazato ,  Yoshiaki Yazawa ,  Masanori Odaka ,  Hideaki Uchida ,  Nobuaki Miyakawa

发明人： Kinya Mitsumoto ,  Shinji Nakazato ,  Yoshiaki Yazawa ,  Masanori Odaka ,  Hideaki Uchida ,  Nobuaki Miyakawa

IPC分类号： G11C11/417 ,  G11C7/10

CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

摘要： A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

摘要翻译： 一种存储器件，其中使用多个阻抗元件分压由最高工作电压下降固定电压的电压，并且公共数据线被分压电压偏置。 由于施加了来自最高工作电位的固定电压降低的电压，即使当阻抗元件的电阻值降低时，流过阻抗元件路径的电流也不会显着增加，并且获得低功耗 。 由于阻抗元件的电阻值降低，所以由寄生于公共数据线的电阻和杂散电容确定的时间常数减小。 因此，与存储在存储单元中的信息对应地产生的公用数据线的电位变化加快，数据检测时间缩短，可以缩短访问时间。

公开(公告)号：US4682200A

公开(公告)日：1987-07-21

申请号：US851485

申请日：1986-04-14

申请人： Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

发明人： Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

IPC分类号： H01L21/8238 ,  G11C11/34 ,  G11C11/419 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/02

CPC分类号： G11C11/419 ,  H01L27/11

摘要： A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.P) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.

摘要翻译： 一种半导体存储器件，其中在互补数据线对D，＆amp; D和D中的串联插入的等效串联电阻在各个互补数据线D，＆amp; L和D之间彼此基本相同。等效串联电阻包括 上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。 维持上拉MISFET（＆upbar＆Qp，＆upbar＆QP）和互补数据线D，＆upbar和D上存在的列切换MISFET（Qy，Qy）的奇偶校验。为了保持这个奇偶校验，形成了两个MISFET 具有相同的形状。 此外，设置与晶体管的接触的布置，使得电流流动的方向和电流路径的长度也相同。 换句话说，铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。