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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4748487A

    公开(公告)日：1988-05-31

    申请号：US053479

    申请日：1987-05-26

    申请人： Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

    发明人： Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

    IPC分类号： H01L21/8238 ,  G11C11/34 ,  G11C11/419 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/02

    CPC分类号： G11C11/419 ,  H01L27/11

    摘要： A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.p) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.

    摘要翻译： 一种半导体存储器件，其中在互补数据线对D，＆amp; D和D中的串联插入的等效串联电阻在各个互补数据线D，＆amp; L和D之间彼此基本相同。等效串联电阻包括 上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。 维持上拉MISFET（Qp，Qp）和在互补数据线D和上拉和下降D上存在的列切换MISFET（Qy，Qy）的奇偶校验。为了保持这个奇偶校验，两个MISFET的形成是 相同的形状。 此外，设置与晶体管的接触的布置，使得电流流动的方向和电流路径的长度也相同。 换句话说，铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。

    Memory device with improved common data line bias arrangement
    3.
    发明授权
    Memory device with improved common data line bias arrangement 失效
    具有改进的公共数据线偏置布置的存储器件

    公开(公告)号：US4829479A

    公开(公告)日：1989-05-09

    申请号：US108623

    申请日：1987-10-15

    申请人： Kinya Mitsumoto ,  Shinji Nakazato ,  Yoshiaki Yazawa ,  Masanori Odaka ,  Hideaki Uchida ,  Nobuaki Miyakawa

    发明人： Kinya Mitsumoto ,  Shinji Nakazato ,  Yoshiaki Yazawa ,  Masanori Odaka ,  Hideaki Uchida ,  Nobuaki Miyakawa

    IPC分类号： G11C11/417 ,  G11C7/10

    CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

    摘要： A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

    摘要翻译： 一种存储器件，其中使用多个阻抗元件分压由最高工作电压下降固定电压的电压，并且公共数据线被分压电压偏置。 由于施加了来自最高工作电位的固定电压降低的电压，即使当阻抗元件的电阻值降低时，流过阻抗元件路径的电流也不会显着增加，并且获得低功耗 。 由于阻抗元件的电阻值降低，所以由寄生于公共数据线的电阻和杂散电容确定的时间常数减小。 因此，与存储在存储单元中的信息对应地产生的公用数据线的电位变化加快，数据检测时间缩短，可以缩短访问时间。

    Semiconductor memory device with matched equivalent series resistances to the complementary data lines
    4.
    发明授权
    Semiconductor memory device with matched equivalent series resistances to the complementary data lines 失效
    半导体存储器件与互补数据线具有匹配的等效串联电阻

    公开(公告)号：US4682200A

    公开(公告)日：1987-07-21

    申请号：US851485

    申请日：1986-04-14

    申请人： Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

    发明人： Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

    IPC分类号： H01L21/8238 ,  G11C11/34 ,  G11C11/419 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/02

    CPC分类号： G11C11/419 ,  H01L27/11

    摘要： A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.P) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.

    摘要翻译： 一种半导体存储器件，其中在互补数据线对D，＆amp; D和D中的串联插入的等效串联电阻在各个互补数据线D，＆amp; L和D之间彼此基本相同。等效串联电阻包括 上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。 维持上拉MISFET（＆upbar＆Qp，＆upbar＆QP）和互补数据线D，＆upbar和D上存在的列切换MISFET（Qy，Qy）的奇偶校验。为了保持这个奇偶校验，形成了两个MISFET 具有相同的形状。 此外，设置与晶体管的接触的布置，使得电流流动的方向和电流路径的长度也相同。 换句话说，铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。

    Write circuit for use in semiconductor storage device
    5.
    发明授权
    Write circuit for use in semiconductor storage device 失效
    用于半导体存储设备的写电路

    公开(公告)号：US4665505A

    公开(公告)日：1987-05-12

    申请号：US685552

    申请日：1984-12-24

    申请人： Nobuaki Miyakawa ,  Yoshiaki Yazawa ,  Shoichi Ozeki ,  Kinya Mitsumoto

    发明人： Nobuaki Miyakawa ,  Yoshiaki Yazawa ,  Shoichi Ozeki ,  Kinya Mitsumoto

    IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/40

    CPC分类号： G11C7/1096 ,  G11C7/1078

    摘要： A write circuit for a semiconductor storage device which comprises a data output stage constructed by a composite circuit including at least one MOS transistor logic circuit and bipolar transistor. The Mos transistor circuit operates in response to an input signal to control the on-off states of at least one of the bipolar transistors. The write circuit implements less power consumption.

    摘要翻译： 一种用于半导体存储装置的写入电路，包括由包括至少一个MOS晶体管逻辑电路和双极晶体管的复合电路构成的数据输出级。 Mos晶体管电路响应于输入信号而工作，以控制至少一个双极晶体管的导通截止状态。 写入电路实现更少的功耗。

    Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels
    7.
    发明授权
    Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels 失效
    用于半导体存储器件的逻辑门电路和并行位测试电路，能够在低电源电平下工作

    公开(公告)号：US5646897A

    公开(公告)日：1997-07-08

    申请号：US426384

    申请日：1995-04-21

    申请人： Seigou Yukutake ,  Masahiro Iwamura ,  Kinya Mitsumoto ,  Takashi Akioka ,  Noboru Akiyama

    发明人： Seigou Yukutake ,  Masahiro Iwamura ,  Kinya Mitsumoto ,  Takashi Akioka ,  Noboru Akiyama

    IPC分类号： G11C7/10 ,  G11C29/34 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C29/028 ,  G11C29/50 ,  G11C7/1051 ,  G11C11/41 ,  G11C2029/5004 ,  G11C29/34

    摘要： A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.

    摘要翻译： 提供了一种用于存储器件的逻辑电路，其可以以比传统器件更低的电压电源电平在高速下操作。 该逻辑电路可以用于执行来自多个预读取放大器的互补逻辑信号的有线或逻辑运算的多位测试电路，通过射极跟随器接收有线或逻辑运算的输出，使用 双极晶体管，并通过电平比较电路输出互补逻辑信号的“与”信号。 还提供读出放大器，用于执行来自多个预读放大器的互补逻辑信号的有线或逻辑运算，通过具有半导体的电平移位电路提高布线或逻辑运算的输出电平 元件，用于对输入信号施加反向偏置电位，执行移位上升输出的线或运算和其他块的输出，以及接收和放大有线逻辑运算的输出。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07623397B2

    公开(公告)日：2009-11-24

    申请号：US11514101

    申请日：2006-09-01

    申请人： Noriyuki Itano ,  Kinya Mitsumoto

    发明人： Noriyuki Itano ,  Kinya Mitsumoto

    IPC分类号： G11C7/00 ,  G11C5/06 ,  G11C8/00 ,  H01L25/00

    CPC分类号： H03L7/0812 ,  G06F1/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20

    摘要： A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.

    摘要翻译： 一种具有与其中的半导体芯片连接的封装电路部分的半导体器件。 半导体芯片包括多个焊盘电极，封装电路部分包括连接到半导体芯片上的焊盘电极的布线，安装端子，以及用于接收从预定的一个焊盘电极输出的信号的第一信号路径， 信号到另一个焊盘电极。 第一信号路径包括延迟元件，该延迟元件与从安装端子中的预定安装端子到另一个安装端子延伸穿过半导体芯片的第二信号路径中的延迟相比较，并且设置在用于相位比较的反馈路径上用于使 从第二信号路径到输入信号到第二信号路径的相位的输出信号的相位。

    Synchronous memory with pipelined write operation
    10.
    发明授权
    Synchronous memory with pipelined write operation 失效
    具有流水线写入操作的同步存储器

    公开(公告)号：US5761150A

    公开(公告)日：1998-06-02

    申请号：US651873

    申请日：1996-05-21

    申请人： Seigoh Yukutake ,  Kinya Mitsumoto ,  Takashi Akioka ,  Masahiro Iwamura ,  Noboru Akiyama

    发明人： Seigoh Yukutake ,  Kinya Mitsumoto ,  Takashi Akioka ,  Masahiro Iwamura ,  Noboru Akiyama

    IPC分类号： G11C11/413 ,  G06F12/00 ,  G11C7/10 ,  G11C8/06 ,  G11C11/401 ,  G11C11/407 ,  G11C11/418 ,  G11C8/00 ,  G11C7/00

    CPC分类号： G11C8/06 ,  G11C11/418 ,  G11C7/1072 ,  G11C2207/2218

    摘要： There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.

    摘要翻译： 提供了一种控制RAM的内部地址信号的方法，其中在芯片上实现了后期写入方法。 为每个地址提供两组用于读取和写入的地址寄存器，并且还在两组地址寄存器之间提供中间寄存器。 中间寄存器由通过获得时钟信号和写入使能信号的AND结果而形成的信号控制，并且用于读取和写入的两组地址寄存器仅由时钟信号控制。 选择电路根据写使能信号选择两组地址寄存器的输出作为输入，以控制内部地址。