公开(公告)号：US07423462B2

公开(公告)日：2008-09-09

申请号：US11489367

申请日：2006-07-18

Applicant: Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

Inventor： Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

IPC: H03L7/06 ,  H03L7/00

CPC classification number: H03L7/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

公开(公告)号：US20070115036A1

公开(公告)日：2007-05-24

申请号：US11652939

申请日：2007-01-12

Applicant: Seong-hoon Lee

Inventor： Seong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03K5/15013 ,  H03K2005/00286 ,  H03L7/0818

Abstract: Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD includes either one or two variable delay lines that provide coarse phase adjustment of an associated input signal. Each HD also includes one or more phase mixers that provide fine phase adjustment of the input signal.

Abstract translation: 提供了使用数字控制分级延迟单元（HD）产生多相时钟信号的电路和方法。 多个串行耦合的HD输出相对于参考时钟信号相移的时钟信号。 每个HD包括提供相关输入信号的粗略相位调整的一个或两个可变延迟线。 每个HD还包括提供输入信号的精细相位调整的一个或多个相位混合器。

公开(公告)号：US20060255847A1

公开(公告)日：2006-11-16

申请号：US11489693

申请日：2006-07-18

Applicant: Adrian Drexler ,  Debra Bell ,  Tyler Gomm ,  Seong-hoon Lee

Inventor： Adrian Drexler ,  Debra Bell ,  Tyler Gomm ,  Seong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

公开(公告)号：US20060255846A1

公开(公告)日：2006-11-16

申请号：US11489369

申请日：2006-07-18

Applicant: Adrian Drexler ,  Debra Bell ,  Tyler Gomm ,  Seong-hoon Lee

Inventor： Adrian Drexler ,  Debra Bell ,  Tyler Gomm ,  Seong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract translation: 时钟捕获同步电路首先从参考时钟信号产生同步的时钟信号，然后捕获同步的时钟信号，并在参考时钟信号被去除之后继续输出同步的时钟信号。 时钟捕获同步电路还减少同步时钟信号中的输入参考抖动。

公开(公告)号：US20060255845A1

公开(公告)日：2006-11-16

申请号：US11489367

申请日：2006-07-18

Applicant: Adrian Drexler ,  Debra Bell ,  Tyler Gomm ,  Seong-hoon Lee

Inventor： Adrian Drexler ,  Debra Bell ,  Tyler Gomm ,  Seong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

公开(公告)号：US07095261B2

公开(公告)日：2006-08-22

申请号：US10840015

申请日：2004-05-05

Applicant: Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

Inventor： Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

IPC: H03L7/06 ,  H03L7/00

CPC classification number: H03L7/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

公开(公告)号：US20060164140A1

公开(公告)日：2006-07-27

申请号：US11313291

申请日：2005-12-20

Applicant: Seong-hoon Lee

Inventor： Seong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03K5/15013 ,  H03K2005/00286 ,  H03L7/0818

Abstract: Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD includes either one or two variable delay lines that provide coarse phase adjustment of an associated input signal. Each HD also includes one or more phase mixers that provide fine phase adjustment of the input signal.

公开(公告)号：US20060071696A1

公开(公告)日：2006-04-06

申请号：US11256215

申请日：2005-10-21

Applicant: Seong-hoon Lee

Inventor： Seong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0814

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.