公开(公告)号：US06853006B2

公开(公告)日：2005-02-08

申请号：US10630978

申请日：2003-07-31

申请人： Mitsuhiro Kataoka ,  Yuuichi Takeuchi ,  Masami Naito ,  Rajesh Kumar ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Mitsuhiro Kataoka ,  Yuuichi Takeuchi ,  Masami Naito ,  Rajesh Kumar ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80 ,  H01L21/04 ,  H01L21/337 ,  H01L29/04 ,  H01L29/24 ,  H01L29/808 ,  H01L31/312

CPC分类号： H01L29/66068 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/8083

摘要： A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is . A trench is formed on the SiC to have a stripe structure extending toward a direction. An SiC epitaxial layer is formed on an inside surface of the trench.

摘要翻译： 碳化硅（SiC）衬底设置有离轴取向{0001}表面，其离轴方向<11-20>。 在SiC上形成沟槽以具有向<11-20>方向延伸的条纹结构。 在沟槽的内表面上形成SiC外延层。

公开(公告)号：US06577260B2

公开(公告)日：2003-06-10

申请号：US09819719

申请日：2001-03-29

申请人： Koji Okada ,  Hiroyuki Matsunami

发明人： Koji Okada ,  Hiroyuki Matsunami

IPC分类号： H03M166

CPC分类号： H03K17/04106 ,  H03K17/162 ,  H03K17/693 ,  H03M1/745

摘要： A Digital/Analog converter comprising a plurality of current sources, and a selecting circuit for selecting a current source from the plurality of current sources on the basis of a digital signal. The selecting circuit includes a first transistor in which the digital signal is supplied. The selecting circuit also includes a second transistor with the same conductivity type as the first transistor for receiving an inverted digital signal of the digital signal. The second transistor is connected to the output of the first transistor.

摘要翻译： 一种数字/模拟转换器，包括多个电流源，以及选择电路，用于根据数字信号从多个电流源中选择电流源。 选择电路包括其中提供数字信号的第一晶体管。 选择电路还包括具有与第一晶体管相同的导电类型的第二晶体管，用于接收数字信号的反相数字信号。 第二晶体管连接到第一晶体管的输出。

公开(公告)号：US07671387B2

公开(公告)日：2010-03-02

申请号：US12179320

申请日：2008-07-24

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

公开(公告)号：US07528426B2

公开(公告)日：2009-05-05

申请号：US11337143

申请日：2006-01-20

申请人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/808

CPC分类号： H01L29/808 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/1608

摘要： A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

摘要翻译： 横向JFET具有包括由n型杂质区形成的n型半导体层（3）和在n型半导体层（3）上由p型杂质区形成的p型半导体层的基本结构， 。 此外，在p型半导体层中，设置有延伸到n型半导体层（3）中的p +型栅极区域（7），并且含有比n的杂质浓度高的p型杂质 型半导体层（3）和与p +型栅极区域（7）间隔预定距离的n +型漏极区域（9），并且含有杂质浓度高于n的n型杂质 型半导体层（3）。 利用这种结构，可以提供横向JFET，其具有进一步降低的导通电阻，同时保持高的击穿电压性能。

公开(公告)号：US07321142B2

公开(公告)日：2008-01-22

申请号：US10544017

申请日：2004-05-21

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80

CPC分类号： H01L29/66901 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/808

摘要： On an SiC single crystal substrate, an electric field relaxation layer and a p− type buffer layer are formed. The electric field relaxation layer is formed between the p− type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p− type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.

摘要翻译： 在SiC单晶衬底上形成电场弛豫层和p型缓冲层。 在p-型缓冲层和SiC单晶衬底之间形成电场弛豫层以接触SiC单晶衬底。 在p型缓冲层上形成n型半导体层。 在n型半导体层上形成p型半导体层。 在p型半导体层中，形成n +型源极区域和n +型漏极区域彼此分开规定的距离。 在n +型源极区域和n +型漏极区域之间的p型半导体层的区域的一部分，形成p +型栅极区域层。

公开(公告)号：US20060113574A1

公开(公告)日：2006-06-01

申请号：US10544017

申请日：2004-05-21

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80

CPC分类号： H01L29/66901 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/808

摘要： On an SiC single crystal substrate, an electric field relaxation layer and a p− type buffer layer are formed. The electric field relaxation layer is formed between the p− type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p− type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.

摘要翻译： 在SiC单晶衬底上形成电场弛豫层和p型缓冲层。 在p-型缓冲层和SiC单晶衬底之间形成电场弛豫层以接触SiC单晶衬底。 在p型缓冲层上形成n型半导体层。 在n型半导体层上形成p型半导体层。 在p型半导体层中，形成n +型源极区域和n +型漏极区域彼此分开规定的距离。 在n +型源极区域和n +型漏极区域之间的p型半导体层的区域的一部分，形成p +型栅极区域层。

公开(公告)号：US07049644B2

公开(公告)日：2006-05-23

申请号：US10496040

申请日：2002-12-02

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80 ,  H01L31/112

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

公开(公告)号：US07023033B2

公开(公告)日：2006-04-04

申请号：US10362345

申请日：2002-06-11

申请人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/808

CPC分类号： H01L29/808 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/1608

摘要： A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

公开(公告)号：US20050093017A1

公开(公告)日：2005-05-05

申请号：US10496040

申请日：2002-12-02

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L21/337 ,  H01L29/808 ,  H01L29/51

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer (18A) arranged in a third semiconductor layer (13) between source/drain region layers (6, 8), having a lower surface extending on the second semiconductor layer (12), and doped with p-type impurities more heavily than the second semiconductor layer (12), and a second gate electrode layer (18B) arranged in a fifth semiconductor layer (15) between the source/drain region layers (6, 8), having a lower surface extending on a fourth semiconductor layer (14), having substantially the same concentration of p-type impurities as the first gate electrode layer (18A), and having the same potential as the first gate electrode layer (18A). Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源极/漏极区域（6,8）之间的第三半导体层（13）中的第一栅极电极层（18A），其具有在第二半导体层（12）上延伸的下表面， 并且掺杂有比第二半导体层（12）更重的p型杂质;以及布置在源极/漏极区域（6,8）之间的第五半导体层（15）中的第二栅电极层（18B） 具有在第四半导体层（14）上延伸的下表面，其具有与第一栅极电极层（18A）大致相同的p型杂质浓度，并具有与第一栅电极层（18A）相同的电位 ）。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。