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31.发明授权公开(公告)号：US06256726B1
公开(公告)日：2001-07-03
申请号：US07979772
申请日：1992-11-20
申请人： Takashi Hotta , Shigeya Tanaka , Hideo Maejima
发明人： Takashi Hotta , Shigeya Tanaka , Hideo Maejima
IPC分类号： G06F938
CPC分类号： G06F9/3889 , G06F9/3802 , G06F9/3824 , G06F9/3842 , G06F9/3851 , G06F9/3885
摘要： The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.
摘要翻译： 用于由管线系统执行由有线逻辑实现的指令的数据处理器包括多个指令寄存器和相同数量的算术运算单元。 一次在一个机器周期中在指令寄存器中读取的多个指令由多个算术运算单元并行处理。
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公开(公告)号：US6029220A
公开(公告)日：2000-02-22
申请号：US957914
申请日：1992-10-08
CPC分类号： G06F9/3875 , G06F9/3869
摘要： A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.
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公开(公告)号：US5680637A
公开(公告)日：1997-10-21
申请号：US599856
申请日：1996-02-13
CPC分类号： G06F9/30189 , G06F9/30043 , G06F9/30079 , G06F9/38 , G06F9/383 , G06F9/3836 , G06F9/3853 , G06F9/3885
摘要： A RISC processor is arranged to reduce a code size, make the hardware less complicated, execute a plurality of operations for one machine cycle, and enhance the performance. The processor is capable of executing N instruction each having a short word length for indicating a single operation or an instruction having a long word length for indicating M (N
摘要翻译： RISC处理器被设置为减少代码大小，使硬件更不复杂，对一个机器周期执行多个操作，并提高性能。 处理器能够执行每个具有用于指示单个操作的短字长的N指令或具有用于指示M（N
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34.发明授权Information processor and information processing system utilizing clock signal 失效信息处理器和利用时钟信号的信息处理系统
公开(公告)号：US5542083A
公开(公告)日：1996-07-30
申请号：US460601
申请日：1995-06-02
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controllled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时 至少一对逻辑器件由时钟信号K1同步控制。
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公开(公告)号：US5784630A
公开(公告)日：1998-07-21
申请号：US367928
申请日：1995-01-03
申请人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
发明人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
CPC分类号： G06F9/3891 , G06F12/084 , G06F15/17381 , G06F15/8015 , G06F9/30087 , G06F9/3009 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3851 , G06F9/3885
摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.
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36.发明授权Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件
公开(公告)号：US5640547A
公开(公告)日：1997-06-17
申请号：US279887
申请日：1994-07-26
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时 至少一对逻辑器件由时钟信号K1同步控制。
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公开(公告)号：US5388249A
公开(公告)日：1995-02-07
申请号：US872174
申请日：1992-04-22
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
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38.发明授权
公开(公告)号：US5233694A
公开(公告)日：1993-08-03
申请号：US433368
申请日：1989-11-08
申请人： Takashi Hotta , Shigeya Tanaka , Hideo Maejima
发明人： Takashi Hotta , Shigeya Tanaka , Hideo Maejima
CPC分类号： G06F9/3889 , G06F9/3802 , G06F9/3824 , G06F9/3842 , G06F9/3851 , G06F9/3885
摘要： The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.
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39.发明授权Information processor and information processing system utilizing clock signal 失效信息处理器和利用时钟信号的信息处理系统
公开(公告)号：US5974560A
公开(公告)日：1999-10-26
申请号：US788831
申请日：1997-01-27
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时 至少一对逻辑器件由时钟信号K1同步控制。
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40.发明授权Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件
公开(公告)号：US5133064A
公开(公告)日：1992-07-21
申请号：US184782
申请日：1988-04-22
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时 至少一对逻辑器件由时钟信号K1同步控制。
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