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    CACHE MEMORY DEVICE, PROCESSOR, AND INFORMATION PROCESSING APPARATUS
    31.
    发明申请
    CACHE MEMORY DEVICE, PROCESSOR, AND INFORMATION PROCESSING APPARATUS 审中-公开
    高速缓存存储器，处理器和信息处理设备

    公开(公告)号：US20130073812A1

    公开(公告)日：2013-03-21

    申请号：US13546274

    申请日：2012-07-11

    申请人： Tatsunori Kanai ,  Tetsuro Kimura ,  Koichi Fujisaki ,  Haruhiko Toyama

    发明人： Tatsunori Kanai ,  Tetsuro Kimura ,  Koichi Fujisaki ,  Haruhiko Toyama

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

    摘要： According to an embodiment, a cache memory device caches data stored in or data to be stored in a memory device. The cache memory device includes a memory area that includes a plurality of cache lines; and a controller. When the number of dirty lines among the cache lines exceeds a predetermined number, the controller writes data of the dirty lines into the memory device, each of the dirty lines containing data that is not written in the memory device.

    摘要翻译： 根据实施例，高速缓冲存储器设备缓存存储在存储设备中的数据或数据。 高速缓冲存储器装置包括：包括多个高速缓存线的存储区; 和控制器。 当高速缓存线中的脏线数量超过预定数量时，控制器将脏线的数据写入存储器件，每条脏线包含未写入存储器件的数据。

    CONTROL DEVICE AND COMPUTER PROGRAM PRODUCT
    32.
    发明申请
    CONTROL DEVICE AND COMPUTER PROGRAM PRODUCT 有权
    控制设备和计算机程序产品

    公开(公告)号：US20120246356A1

    公开(公告)日：2012-09-27

    申请号：US13334235

    申请日：2011-12-22

    申请人： Akihiro Shibata ,  Koichi Fujisaki ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Satoshi Shirai ,  Masaya Tarui ,  Hiroyoshi Haruki

    发明人： Akihiro Shibata ,  Koichi Fujisaki ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Satoshi Shirai ,  Masaya Tarui ,  Hiroyoshi Haruki

    IPC分类号： G06F13/24

    CPC分类号： G06F1/3243 ,  G06F9/4812 ,  Y02D10/152 ,  Y02D10/24

    摘要： According to an embodiment, a control device includes a receiving unit configured to receive an interrupt request requesting an interrupt process to be executed by a processing device that executes one or more processes; a storage unit configured to store therein the interrupt request; a determining unit configured to determine a state of the processing device; a sending unit configured to send the interrupt request to the processing device; and a control unit configured to store the interrupt request received by the receiving unit in the storage unit when the processing device is determined by the determining unit to be in an idle state in which the processing device is not executing the processes and a predetermined condition is not satisfied, and to control the sending unit to send the interrupt request stored in the storage unit to the processing device when the predetermined condition is satisfied.

    摘要翻译： 根据实施例，控制装置包括：接收单元，被配置为接收请求由执行一个或多个处理的处理装置执行的中断处理的中断请求; 存储单元，被配置为在其中存储中断请求; 确定单元，被配置为确定所述处理装置的状态; 发送单元，被配置为将所述中断请求发送到所述处理装置; 以及控制单元，被配置为当所述处理设备被所述确定单元确定为处于处理设备未执行所述处理的空闲状态时，将所述接收单元接收到的所述中断请求存储在所述存储单元中，并且预定条件是 并且当满足预定条件时，控制发送单元将存储在存储单元中的中断请求发送到处理装置。