公开(公告)号：US20150058662A1

公开(公告)日：2015-02-26

申请号：US14331575

申请日：2014-07-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G06F11/10 ,  G06F12/02 ,  G11C29/52

CPC classification number: G06F11/108 ,  G06F3/06 ,  G06F12/0246 ,  G11C2029/0411

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, includes at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.

Abstract translation: 用于访问由仲裁器执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 在第一批中将数据发送到连接到存储单元访问接口中的一个的第一存储单元之后，仲裁器向每个第一存储单元发出数据写入命令，从而使得每个第一存储单元能够启动物理数据编程。 在每个第一存储单元的物理数据编程期间，数据被发送到第二存储单元，每个存储单元在第二批中连接到一个存储单元访问接口。

公开(公告)号：US20240152288A1

公开(公告)日：2024-05-09

申请号：US18412635

申请日：2024-01-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F3/06 ,  G06F12/02 ,  G11C11/56

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G11C11/5628 ,  G11C11/5642 ,  G06F2212/7201 ,  G06F2212/7206 ,  Y02D10/00

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US11080203B2

公开(公告)日：2021-08-03

申请号：US16573409

申请日：2019-09-17

Applicant: Silicon Motion, Inc.

Inventor： Yang-Chih Shen ,  Shih-Chang Chang

IPC: G06F12/1009 ,  G06F12/0802 ,  G06F12/02

Abstract: High performance data storage device is disclosed, which has a memory controller dynamically updating mapping information on the temporary storage to manage physical space information mapped to a logical address recognized by a host. The memory controller uses a first bit to an Nth bit of the physical space information to indicate a physical space of the non-volatile memory or a cache address of the data cache space, without using additional bits to map the physical space information to the non-volatile memory or the data cache space, where N is a number greater than one. Among numbers formed by the first to the Nth bit, the memory controller uses numbers corresponding to non-existent physical space of the non-volatile memory to map the physical space information to the non-volatile memory or the data cache space.

公开(公告)号：US10990325B2

公开(公告)日：2021-04-27

申请号：US16590398

申请日：2019-10-02

Applicant: Silicon Motion Inc.

Inventor： Yu-Han Hsiao ,  Yang-Chih Shen ,  Huan-Jung Yeh

IPC: G06F3/06 ,  G06F12/0804 ,  G06F12/08

Abstract: A write control method, an associated data storage device and the controller thereof are provided. The write control method includes: receiving one or more commands from a host device and executing the one or more commands, and performing determining operations to generate determining results; in response to the determining results, starting performing write collection; collecting and handling one or more write commands to buffer data of the one or more write commands through a buffer memory, and performing other determining operations to generate other determining results; in response to the other determining results, according to a quantity of one or more collected and handled write commands, determining whether data thereof has filled up a write buffer region of the buffer memory; and in response to the data having filled up the write buffer region, flushing the write buffer region to write the data therein into a non-volatile memory.

公开(公告)号：US10725902B2

公开(公告)日：2020-07-28

申请号：US16031598

申请日：2018-07-10

Applicant: Silicon Motion, Inc.

Inventor： Yang-Chih Shen

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1027

Abstract: A method for scheduling read commands, performed by a processing unit, includes at least the following steps: receiving a logical read command and a logical address; obtaining a high-level mapping table; obtaining a mapping table block according to the logical address and the high-level mapping table; obtaining a first physical address according to the logical address and the mapping table block; outputting an actual read command and the first physical address to a storage unit to obtain a data; and outputting the data which is responsive to the logical read command. The high-level mapping table includes a plurality of records, and one of the records is utilized to illustrate a second physical address of the mapping table block.

公开(公告)号：US10235075B2

公开(公告)日：2019-03-19

申请号：US15985718

申请日：2018-05-22

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G11C11/34 ,  G11C16/04 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode.

公开(公告)号：US20180322044A1

公开(公告)日：2018-11-08

申请号：US16031598

申请日：2018-07-10

Applicant: Silicon Motion, Inc.

Inventor： Yang-Chih Shen

IPC: G06F12/02 ,  G06F12/1009 ,  G06F12/1027

Abstract: A method for scheduling read commands, performed by a processing unit, includes at least the following steps: receiving a logical read command and a logical address; obtaining a high-level mapping table; obtaining a mapping table block according to the logical address and the high-level mapping table; obtaining a first physical address according to the logical address and the mapping table block; outputting an actual read command and the first physical address to a storage unit to obtain a data; and outputting the data which is responsive to the logical read command. The high-level mapping table includes a plurality of records, and one of the records is utilized to illustrate a second physical address of the mapping table block.

公开(公告)号：US20180260132A1

公开(公告)日：2018-09-13

申请号：US15802065

申请日：2017-11-02

Applicant: Silicon Motion, Inc.

Inventor： Ting-Hsing Wang ,  Yang-Chih Shen

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/02 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A data storage device with a non-volatile memory on which a garbage collection operation is segmented to be accomplished at separate time intervals. Host commands are inserted to be executed between the separate time intervals. A data swap stage or/and an F2H table update stage or/and an H2F table update stage for a garbage collection operation may be segmented to be performed at separate time intervals.

公开(公告)号：US10007460B2

公开(公告)日：2018-06-26

申请号：US15643501

申请日：2017-07-07

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G11C11/34 ,  G11C16/04 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US09990280B2

公开(公告)日：2018-06-05

申请号：US14702392

申请日：2015-05-01

Applicant: Silicon Motion, Inc.

Inventor： Yang-Chih Shen

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1041 ,  G06F2212/7203

Abstract: A method for reading data from a storage unit of a flash memory, performed by a processing unit, including at least the following steps: A first read command is received from a master device via a first access interface. It is determined whether data requested by the first read command has been cached in a first buffer, which caches continuous data obtained from a storage unit. A second access interface is directed to read the data requested by the first read command from the storage unit and store the read data in a second buffer and the first access interface is directed to read the data requested by the first read command from the second buffer and clock the read data out to the master device when data requested by the first read command has not been cached in the first buffer.