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31.发明授权公开(公告)号：US11600321B2
公开(公告)日：2023-03-07
申请号：US16987101
申请日：2020-08-06
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Stephen Trinh , Stanley Hong , Anh Ly , Vipin Tiwari
Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.
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公开(公告)号：US11507642B2
公开(公告)日：2022-11-22
申请号：US16449201
申请日：2019-06-21
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Stephen Trinh , Thuan Vu , Stanley Hong , Vipin Tiwari , Mark Reiten , Nhan Do
Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.
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公开(公告)号：US11500442B2
公开(公告)日：2022-11-15
申请号：US16353830
申请日：2019-03-14
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Vipin Tiwari , Mark Reiten , Nhan Do
Abstract: Numerous embodiments are disclosed for converting neuron current output by a vector-by-matrix multiplication (VMM) array into neuron current-based time pulses and providing such pulses as an input to another VMM array within an artificial neural network. Numerous embodiments are disclosed for converting the neuron current-based time pulses into analog current or voltage values if an analog input is needed for the VMM array.
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公开(公告)号：US20210407588A1
公开(公告)日：2021-12-30
申请号：US17471099
申请日：2021-09-09
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Steven Lemke , Vipin Tiwari , Nhan Do , Mark Reiten
IPC: G11C11/54 , H01L27/11521 , H01L29/423 , G11C16/04 , G06N3/04 , G11C16/10 , G11C16/14 , H01L29/788
Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.
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公开(公告)号：US20210090654A1
公开(公告)日：2021-03-25
申请号：US17095661
申请日：2020-11-11
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Steven Lemke , Nhan Do , Vipin Tiwari , Mark Reiten
Abstract: Numerous embodiments are disclosed for providing temperature compensation in an analog memory array. A method and related system are disclosed for compensating for temperature changes in an array of memory cells by measuring an operating temperature within the array of memory cells and changing a threshold voltage of a selected memory cell in the array of memory cells to compensate for a change in the operating temperature.
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Patent Agency Ranking
公开(公告)号：US10943661B2
公开(公告)日：2021-03-09
申请号：US16550253
申请日：2019-08-25
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Stanley Hong , Anh Ly , Vipin Tiwari , Nhan Do
IPC: G11C16/04 , G06N3/08 , H01L27/11521 , H01L29/788 , G06N3/04
Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
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37.发明申请公开(公告)号：US20200349422A1
公开(公告)日：2020-11-05
申请号：US16449205
申请日：2019-06-21
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Stephen Trinh , Thuan Vu , Stanley Hong , Vipin Tiwari , Mark Reiten , Nhan Do
Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.
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38.发明授权公开(公告)号：US10741568B2
公开(公告)日：2020-08-11
申请号：US16231231
申请日：2018-12-21
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Steven Lemke , Vipin Tiwari , Nhan Do , Mark Reiten
IPC: G06N3/04 , G06F3/06 , H01L27/115 , H01L29/788 , H01L27/11531 , G06N3/08 , G11C16/04
Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
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39.发明申请公开(公告)号：US20200233482A1
公开(公告)日：2020-07-23
申请号：US16354040
申请日：2019-03-14
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Vipin Tiwari , Mark Reiten , Nhan Do
IPC: G06F1/3234 , G11C16/04 , G11C11/54 , G06F17/16 , G06N3/08
Abstract: Numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.
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公开(公告)号：US10586598B2
公开(公告)日：2020-03-10
申请号：US16025039
申请日：2018-07-02
Applicant: Silicon Storage Technology, Inc.
Inventor： Vipin Tiwari , Nhan Do
Abstract: A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.
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