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公开(公告)号：US07827471B2
公开(公告)日：2010-11-02
申请号：US11581055
申请日：2006-10-12
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6516
摘要： A method is described for use in determining a residue of a message. The method includes loading at least a portion of each of a set of polynomials derived from a first polynomial, g(x), and determining the residue using a set of stages. Individual ones of the stages apply a respective one of the derived set of polynomials to data output by a preceding one of the set of stages.
摘要翻译： 描述了一种用于确定消息的残差的方法。 该方法包括加载从第一多项式g（x）导出的一组多项式中的每一个的至少一部分，并使用一组级确定残差。 各个阶段中的各个阶段将所导出的多项式集合中的相应一个应用于由所述一组阶段中的前一个输出的数据。
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公开(公告)号：US20070297601A1
公开(公告)日：2007-12-27
申请号：US11476432
申请日：2006-06-27
IPC分类号： H04L9/28
CPC分类号： G06F7/72
摘要： Techniques are described to determine N mod M, where N is a number having a width of n-bits, and M is a number having a width of m-bits. The techniques, generally, involve determining N′=NH2f mod M+NL and, subsequently, determining N′ mod M
摘要翻译： 描述技术来确定N mod M，其中N是具有n位宽度的数，M是具有m位宽度的数。 这些技术通常涉及确定N'= N H 2 H 2 mod M + N L L，并且随后确定N'mod M
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33.发明授权Hardware compilation and/or translation with fault detection and roll back functionality 有权具有故障检测和回滚功能的硬件编译和/或翻译公开(公告)号：US08893094B2
公开(公告)日：2014-11-18
申请号：US13341812
申请日：2011-12-30
CPC分类号： G06F8/44 , G06F9/3001 , G06F9/30087 , G06F9/30174 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/462 , G06F11/0751
摘要： Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states.
摘要翻译： 公开了具有故障检测和回滚功能的硬件编译和/或翻译。 编译和/或翻译逻辑接收以一种语言编码的程序，并且将该程序编码成包括指令的第二语言，以支持未被编码为程序的原始语言编码的处理器特征。 在一个实施例中，执行单元执行包括执行第一操作的操作检查指令的第二语言的指令并记录用于比较的第一操作结果，以及执行第二操作和故障检测操作的操作测试指令 通过比较第二操作结果与记录的第一操作结果。 在一些实施例中，执行单元执行第二语言的指令，包括提交指令以记录映射到架构寄存器的寄存器的执行检查点状态，以及回滚指令，将映射到架构寄存器的寄存器恢复到先前记录的执行检查点状态。
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公开(公告)号：US20110264720A1
公开(公告)日：2011-10-27
申请号：US11323994
申请日：2005-12-30
申请人： Wajdi Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译： 通常，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的组具有访问第一操作数和第二操作数以乘以具有多个段的第一操作数和第二操作数 具有多个段的操作数。 所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的相应一个，直到所述第二 操作数已被提供给第一个操作数的每个段。 该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器中的不同乘法器的输出。 乘法器还包括耦合到逻辑的累加器。
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35.发明授权Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit 失效通过ALU访问使用范围索引访问不同范围的变量的执行指令在过程调用和退出时自动更改公开(公告)号：US07475229B2
公开(公告)日：2009-01-06
申请号：US11354670
申请日：2006-02-14
申请人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel F. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel F. Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F9/302
CPC分类号： G06F21/602
摘要： In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.
摘要翻译： 通常，在一个方面，本公开描述了一种处理单元，其包括存储器，算术逻辑单元和具有访问控制存储器的程序指令的控制逻辑。 控制逻辑包括访问多组变量的逻辑，不同变量集合中的变量由指令相同地引用，将变量集合中的一个与当前由算术执行的指令中使用的变量集合相关联 逻辑单元，响应于过程调用或退出而改变与当前变量集相关联的变量集合，并且改变一组变量的值，而不是与当前变量集合相关联的变量集合 响应一个指令。
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公开(公告)号：US20070299899A1
公开(公告)日：2007-12-27
申请号：US11476329
申请日：2006-06-27
IPC分类号： G06F7/52
CPC分类号： G06F7/5324
摘要： Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.
摘要翻译： 技术被描述为将两个数字A和B相乘。通常，通过对A和B的段使用Karatsuba乘法来执行乘法，并且基于A和B的最高有效位的值来调整Karatsuba乘法。
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公开(公告)号：US20140215162A1
公开(公告)日：2014-07-31
申请号：US13995283
申请日：2011-12-28
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0817 , G06F12/0846 , G06F13/00 , G06F13/10 , G06F13/385
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining a last accessor of the memory address, sending a cache probe to the last accessor, determining the last accessor no longer has a copy of the line; and sending a request for the previously accessed version of the line. The request may bypass the tag-directories and obtain the requested data from memory.
摘要翻译： 多核处理装置可以提供高速缓存探针和数据检索方法。 该方法可以包括将请求者的存储器请求发送到记录保存结构。 存储器请求可以具有存储请求的数据的存储器的存储器地址。 该方法还可以包括确定存储器地址的最后存取器，向最后一个存取器发送高速缓存探测器，确定最后一个访问器不再具有该行的副本; 并发送对先前访问版本的行的请求。 该请求可以绕过标签目录并从存储器获取所请求的数据。
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公开(公告)号：US20140006716A1
公开(公告)日：2014-01-02
申请号：US13993779
申请日：2011-12-29
IPC分类号： G06F12/08
摘要： In some implementations, a shared cache structure may be provided for sharing data among a plurality of processor cores. A data structure may be associated with the shared cache structure, and may include a plurality of entries, with each entry corresponding to one of the cache lines in the shared cache. Each entry in the data structure may further include a field to identify a processor core that most recently requested the data of the cache line corresponding to the entry. When a request for a particular cache line is received, a request for the data may be sent to a particular processor core identified in the data structure as the last accessor of the data.
摘要翻译： 在一些实现中，可以提供共享高速缓存结构以在多个处理器核之间共享数据。 数据结构可以与共享缓存结构相关联，并且可以包括多个条目，其中每个条目对应于共享高速缓存中的一条高速缓存行。 数据结构中的每个条目还可以包括用于标识最近请求与该条目对应的高速缓存线的数据的处理器核心的字段。 当接收到对特定高速缓存行的请求时，可以将数据请求发送到数据结构中标识的特定处理器核心作为数据的最后访问器。
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公开(公告)号：US08229109B2
公开(公告)日：2012-07-24
申请号：US11476432
申请日：2006-06-27
IPC分类号： G06F7/72
CPC分类号： G06F7/72
摘要： Techniques are described to determine N mod M, where N is a number having a width of n-bits, and M is a number having a width of m-bits. The techniques, generally, involve determining N′=Nrt2f mod M+NL and, subsequently, determining N′ mod M.
摘要翻译： 描述技术来确定N mod M，其中N是具有n位宽度的数，M是具有m位宽度的数。 这些技术通常涉及确定N'= Nrt2f mod M + NL，并且随后确定N'mod M.
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公开(公告)号：US07930337B2
公开(公告)日：2011-04-19
申请号：US11476329
申请日：2006-06-27
IPC分类号： G06F7/52
CPC分类号： G06F7/5324
摘要： Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.
摘要翻译： 技术被描述为将两个数字A和B相乘。通常，通过对A和B的段使用Karatsuba乘法来执行乘法，并且基于A和B的最高有效位的值来调整Karatsuba乘法。
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