公开(公告)号：US06490199B2

公开(公告)日：2002-12-03

申请号：US09867899

申请日：2001-05-30

申请人： Byeong-Hoon Lee ,  Young-Ho Lim

发明人： Byeong-Hoon Lee ,  Young-Ho Lim

IPC分类号： G11C1606

CPC分类号： G11C16/28

摘要： A sense amplifier circuit for a flash memory device of the present invention includes first and second pre-charge circuits for pre-charging a data line (or bit line connected electrically to the data line). The first and second pre-charge circuits are each connected to the data line. The first pre-charge circuit provides a current changed by a fluctuation of the data line voltage to the data line, and the second pre-charge circuit provides a constant voltage regardless of the fluctuation of the data line voltage to the data line. The sense amplifier minimizes the time required to pre-charge the data line (or bit line) to a desired voltage.

摘要翻译： 本发明的闪存器件的读出放大器电路包括用于对数据线（或与数据线电连接的位线）进行预充电的第一和第二预充电电路。 第一和第二预充电电路各自连接到数据线。 第一预充电电路提供由数据线电压向数据线的波动而改变的电流，并且第二预充电电路提供恒定电压，而不管数据线电压对数据线的波动。 读出放大器将数据线（或位线）预充电所需的时间最小化到所需的电压。

公开(公告)号：US6084800A

公开(公告)日：2000-07-04

申请号：US389279

申请日：1999-09-02

申请人： Soo-Hwan Choi ,  Young-Ho Lim

发明人： Soo-Hwan Choi ,  Young-Ho Lim

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C16/30

CPC分类号： G11C16/30

摘要： Disclosed is a circuit of boosting a voltage which comprises a driver circuit for generating a kick signal for driving word lines via row decoder circuits in an array of flash memory cells during read and program modes of operation. The driver circuit makes both electrodes of a large booster capacitor have the same voltage in order to allow a small charge pump to further pump up the word line voltage during programming.

摘要翻译： 公开了一种升压电压的电路，其包括用于在读取和编程操作模式期间通过闪存单元阵列中的行解码器电路产生用于驱动字线的触发信号的驱动器电路。 驱动电路使大型升压电容器的两个电极具有相同的电压，以便在编程期间允许小电荷泵进一步提高字线电压。

公开(公告)号：US08234440B2

公开(公告)日：2012-07-31

申请号：US13239494

申请日：2011-09-22

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7203

摘要： A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.

摘要翻译： 非易失性半导体存储器件包括具有多个存储体的存储单元阵列和与多个存储体中的每一个对应的高速缓存块。 高速缓存块具有预定的数据存储容量。 包括对应于多个存储体中的每一个的页面缓冲器。 编程电路使用页面数据对除了最后的所述存储体之外的所有多个存储体进行编程。 页面数据通过每个页面缓冲器加载并被编程到每个缓存块中，使得当最后一个存储体的页面数据被加载到页面缓冲器中时，加载的页面数据和编入各个缓存块中的页面数据被编程到相应的对应的 银行。

公开(公告)号：US07944747B2

公开(公告)日：2011-05-17

申请号：US12400123

申请日：2009-03-09

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C16/06

CPC分类号： G11C7/12 ,  G11C7/1006 ,  G11C16/04 ,  G11C16/10 ,  G11C29/50 ,  G11C2029/5006 ,  G11C2216/14

摘要： Provided is a method for programming a flash memory device. The method includes receiving writing data, detecting leakage bit lines of the flash memory device, and updating the received writing data in order for data corresponding to the leakage bit lines to be modified as program-inhibit data. A programming operation is performed on the flash memory device after updating the writing data.

摘要翻译： 提供了一种用于对闪存设备进行编程的方法。 该方法包括接收写入数据，检测闪速存储器件的泄漏位线，以及更新所接收的写入数据，以便将与泄漏位线对应的数据修改为编程禁止数据。 在更新写入数据之后，对闪存设备执行编程操作。

公开(公告)号：US20110069543A1

公开(公告)日：2011-03-24

申请号：US12956357

申请日：2010-11-30

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deong Suh

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deong Suh

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/16

摘要： Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing even-numbered nonvolatile memory cells in the first string and then selectively erasing the odd-numbered nonvolatile memory cells in the first string, which may be interleaved with the even-numbered nonvolatile memory cells. This operation to selectively erase the even-numbered nonvolatile memory cells may include erasing the even-numbered nonvolatile memory cells while simultaneously biasing the odd-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the odd-numbered nonvolatile memory cells. The operation to selectively erase the odd-numbered nonvolatile memory cells may include erasing the odd-numbered nonvolatile memory cells while simultaneously biasing the even-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the even-numbered nonvolatile memory cells.

摘要翻译： 操作电荷阱非易失性存储装置的方法包括通过选择性地擦除第一串中的偶数非易失性存储单元然后选择性地擦除第一串中的奇数非易失性存储单元来擦除第一串非易失性存储单元的操作， 可以与偶数非易失性存储单元进行交织。 选择性地擦除偶数非易失性存储单元的操作可以包括擦除偶数非易失性存储单元，同时在禁止奇数非易失性存储单元擦除的阻塞状态下同时偏置奇数非易失性存储单元。 选择性地擦除奇数非易失性存储单元的操作可以包括擦除奇数非易失性存储单元，同时在阻止偶数非易失性存储单元擦除的阻塞状态下同时偏置偶数非易失性存储单元。

公开(公告)号：US20110044108A1

公开(公告)日：2011-02-24

申请号：US12939251

申请日：2010-11-04

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/12 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.

摘要翻译： 闪速存储器和闪速存储器的编程方法包括对字线施加通过电压以升高被释放到接地电压的通道电压。 一个编程电压被施加到所选择的字线，并且当编程电压被施加到所选择的字线时，局部电压被施加到提供有通过电压的至少一个字线。 局部电压低于通过电压，等于或高于接地电压。 在将编程电压施加到所选择的字线之前，升压的通道电压可以被放电。

公开(公告)号：US07821836B2

公开(公告)日：2010-10-26

申请号：US12166364

申请日：2008-07-02

申请人： Moo-Sung Kim ,  Young-Ho Lim

发明人： Moo-Sung Kim ,  Young-Ho Lim

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/20 ,  G11C16/32

摘要： A flash memory device which includes a memory cell array which stores data and trim information, and control logic which controls programming, erasing, and reading modes of the memory cell array. The control logic is operative to receive the trim information from the memory cell array in a power-up mode, and to optimize operational time periods of the programming, erasing, and reading modes in accordance with the trim information.

摘要翻译： 包括存储数据和修剪信息的存储单元阵列的闪速存储器件，以及控制存储单元阵列的编程，擦除和读取模式的控制逻辑。 控制逻辑可操作以在上电模式下从存储器单元阵列接收修剪信息，并且根据修剪信息优化编程，擦除和读取模式的操作时间段。

公开(公告)号：US07773419B2

公开(公告)日：2010-08-10

申请号：US12366266

申请日：2009-02-05

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US07724575B2

公开(公告)日：2010-05-25

申请号：US12035028

申请日：2008-02-21

申请人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

发明人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： In one aspect a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

摘要翻译： 在一个方面，提供可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

公开(公告)号：US20090147575A1

公开(公告)日：2009-06-11

申请号：US12366266

申请日：2009-02-05

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C16/00 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件以及NOR闪存器件中的数据位检测方法中，器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。