公开(公告)号：US20070201277A1

公开(公告)日：2007-08-30

申请号：US11789624

申请日：2007-04-25

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

公开(公告)号：US20060215449A1

公开(公告)日：2006-09-28

申请号：US11263716

申请日：2005-11-01

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US07773419B2

公开(公告)日：2010-08-10

申请号：US12366266

申请日：2009-02-05

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US20090147575A1

公开(公告)日：2009-06-11

申请号：US12366266

申请日：2009-02-05

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C16/00 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件以及NOR闪存器件中的数据位检测方法中，器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US07227790B2

公开(公告)日：2007-06-05

申请号：US11263716

申请日：2005-11-01

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C7/06

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US20070053228A1

公开(公告)日：2007-03-08

申请号：US11482447

申请日：2006-07-07

申请人： Sang-Wan Nam ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Dae-Han Kim

IPC分类号： G11C5/14

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/12

摘要： A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit for selecting one constant voltage among the plurality of the constant voltages and applying the selected one constant voltage to the memory cell array. The voltage generating circuit discharges a leakage current input by the selection circuit through a voltage division path, which generates the constant voltages.

摘要翻译： 一种闪存器件及其电压产生电路。 闪存包括配置有多个存储单元的存储单元阵列，用于产生施加到存储单元阵列的多个恒定电压的电压产生电路，以及用于选择多个存储单元中的一个恒定电压的选择电路 将所选择的一个恒定电压施加到存储单元阵列。 电压产生电路通过分压路径对由选择电路输入的漏电流进行放电，产生恒定电压。

公开(公告)号：US07372747B2

公开(公告)日：2008-05-13

申请号：US11482447

申请日：2006-07-07

申请人： Sang-Wan Nam ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Dae-Han Kim

IPC分类号： G11C5/14

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/12

摘要： A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit for selecting one constant voltage among the plurality of the constant voltages and applying the selected one constant voltage to the memory cell array. The voltage generating circuit discharges a leakage current input by the selection circuit through a voltage division path, which generates the constant voltages.

摘要翻译： 一种闪存器件及其电压产生电路。 闪存包括配置有多个存储单元的存储单元阵列，用于产生施加到存储单元阵列的多个恒定电压的电压产生电路，以及用于选择多个存储单元中的一个恒定电压的选择电路 将所选择的一个恒定电压施加到存储单元阵列。 电压产生电路通过分压路径对由选择电路输入的漏电流进行放电，产生恒定电压。

公开(公告)号：US07885118B2

公开(公告)日：2011-02-08

申请号：US12401784

申请日：2009-03-11

申请人： Sang-Wan Nam ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Dae-Han Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/30 ,  G11C5/145

摘要： Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The reference voltage generating circuit is configured to generate at least one reference voltage to be supplied to the high voltage generating circuit. The reference voltage generating circuit includes a first reference voltage generator configured to generate a first reference voltage in response to a supply voltage, and a second reference voltage generator configured to generate a second reference voltage in response to the first reference voltage. The at least one reference voltage supplied to the high voltage generating circuit includes the second reference voltage.

摘要翻译： 公开了一种闪速存储器件，其包括存储器芯，高电压产生电路和参考电压产生电路。 高电压产生电路被配置为产生要提供给存储器芯的高电压。 参考电压产生电路被配置为产生要提供给高电压发生电路的至少一个参考电压。 参考电压产生电路包括被配置为响应于电源电压产生第一参考电压的第一参考电压发生器和被配置为响应于第一参考电压产生第二参考电压的第二参考电压发生器。 提供给高电压产生电路的至少一个参考电压包括第二参考电压。

公开(公告)号：US07738309B2

公开(公告)日：2010-06-15

申请号：US11946359

申请日：2007-11-28

申请人： Hong-Soo Jeon ,  Dae-Han Kim

发明人： Hong-Soo Jeon ,  Dae-Han Kim

IPC分类号： G11C17/18

CPC分类号： G11C16/28

摘要： A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in response to a cell selection signal and a fuse word-line enable signal, the fuse word-line enable signal being activated after the read enable signal by a first delay time. The row decoder decodes the read voltage in response to a row address signal to generate a decoded read voltage, and to provide the decoded read voltage to a memory cell array.

摘要翻译： 非易失性半导体存储器件包括读电压产生电路，闪存单元熔丝电路和行解码器。 读取电压产生电路响应于读取使能信号和修剪码产生读取电压。 闪存单元熔丝电路响应于单元选择信号和熔丝字线使能信号而生成修整代码，保险丝字线使能信号在读使能信号之后被激活第一延迟时间。 行解码器响应于行地址信号解码读取电压以产生解码的读取电压，并将解码的读取电压提供给存储器单元阵列。

公开(公告)号：US07486573B2

公开(公告)日：2009-02-03

申请号：US11520803

申请日：2006-09-14

申请人： Hong-Soo Jeon ,  Dae-Han Kim

发明人： Hong-Soo Jeon ,  Dae-Han Kim

IPC分类号： G11C5/14

CPC分类号： G11C16/30 ,  G11C11/5642

摘要： A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.

摘要翻译： 闪存器件可以包括存储器单元阵列。 存储单元阵列可以包括多个存储单元。 闪存器件还可以包括产生多个恒定电压的电压发生器。 电压发生器可以包括多个电压调节器，其中每个电压调节器被配置为分离从电荷泵产生的高电压以产生其间具有恒定电压差的至少两个恒定电压。 多个电压调节器可以具有独立的分压路径，其中每个路径被配置为产生单独的恒定电压。