公开(公告)号：US07773419B2

公开(公告)日：2010-08-10

申请号：US12366266

申请日：2009-02-05

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US20090147575A1

公开(公告)日：2009-06-11

申请号：US12366266

申请日：2009-02-05

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C16/00 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件以及NOR闪存器件中的数据位检测方法中，器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US07227790B2

公开(公告)日：2007-06-05

申请号：US11263716

申请日：2005-11-01

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C7/06

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US20070201277A1

公开(公告)日：2007-08-30

申请号：US11789624

申请日：2007-04-25

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

公开(公告)号：US20060215449A1

公开(公告)日：2006-09-28

申请号：US11263716

申请日：2005-11-01

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US20120307560A1

公开(公告)日：2012-12-06

申请号：US13465246

申请日：2012-05-07

申请人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

发明人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： A non-volatile memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path.

摘要翻译： 非易失性存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离的锁存器输出路径。

公开(公告)号：US08174888B2

公开(公告)日：2012-05-08

申请号：US12752213

申请日：2010-04-01

申请人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

发明人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

摘要翻译： 在一个方面，提供一种可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

公开(公告)号：US07864582B2

公开(公告)日：2011-01-04

申请号：US12191434

申请日：2008-08-14

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/16

摘要： Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells. The operation to selectively erase the second plurality of nonvolatile memory cells may include erasing the second plurality of nonvolatile memory cells while simultaneously biasing the first plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the first plurality of nonvolatile memory cells.

摘要翻译： 操作电荷阱非易失性存储装置的方法包括通过选择性地擦除第一串中的第一多个非易失性存储单元，然后选择性地擦除第一串中的第二多个非易失性存储单元来擦除第一串非易失性存储单元的操作， 其可以与第一多个非易失性存储器单元交错。 选择性地擦除第一多个非易失性存储单元的操作可以包括擦除第一多个非易失性存储单元，同时在禁止擦除第二多个非易失性存储单元的阻塞条件下同时偏置第二多个非易失性存储单元。 选择性地擦除第二多个非易失性存储单元的操作可以包括擦除第二多个非易失性存储单元，同时在禁止擦除第一多个非易失性存储单元的阻塞条件下同时偏置第一多个非易失性存储单元。

公开(公告)号：US07839691B2

公开(公告)日：2010-11-23

申请号：US12571980

申请日：2009-10-01

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/349

摘要： A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

摘要翻译： 非易失性半导体存储器件包括：连接到相应位线的单元串; 每个单元串具有连接到串选择线的串选择晶体管，连接到接地选择线的接地选择晶体管和连接到对应字线并且串联连接在串选择晶体管和接地选择晶体管之间的存储单元 ; 第一电压降电路，被配置为在读取操作期间减小施加的读取电压; 配置为减小所施加的读取电压的第二电压降电路; 串行选择线驱动电路，被配置为利用由第一压降电路提供的降低的电压驱动串选择线; 以及接地选择线驱动电路，被配置为用由第二压降电路提供的降低的电压来驱动接地选择线。

公开(公告)号：US20100259982A1

公开(公告)日：2010-10-14

申请号：US12822246

申请日：2010-06-24

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C8/10 ,  G11C8/12 ,  G11C29/806 ,  G11C29/844

摘要： A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.

摘要翻译： 闪速存储器件包括多个存储器块，被配置为响应于块选择信号来选择至少一个存储器块的解码器，被配置为响应于块地址产生块选择信号并且产生标志信号的控制器， 块地址对应于坏块，并且输出缓冲器被配置为响应于指示块地址对应于坏块的标志信号输出固定数据。 当块地址对应于坏块时，控制器产生块选择信号以使解码器中断对应于块地址的存储块的选择。