公开(公告)号：US20130121425A1

公开(公告)日：2013-05-16

申请号：US13665343

申请日：2012-10-31

Applicant: Texas Instruments Incorporated

Inventor： Tarkesh Pande ,  Ramanuja Vedantham ,  Il Han Kim ,  Anand G. Dabak

IPC: H04B3/54

CPC classification number: H04B3/544 ,  H04B3/54 ,  H04B3/542 ,  H04B2203/5408 ,  H04L12/2803 ,  H04L12/2836 ,  H04L12/413 ,  H04L41/0896 ,  H04L47/36 ,  H04L47/765 ,  H04L2012/2843

Abstract: Systems and methods for implementing coexistence by requesting access to a channel in power line communications (PLC) are described. In an illustrative embodiment, a method performed by a PLC device, such as a PLC meter, may include detecting a communication from foreign PLC device on a PLC network in response to a foreign preamble received by the PLC device, determining whether a threshold back-off duration has been reached, and transmitting a channel access request in response to a determination that the threshold back-off duration has been reached.

公开(公告)号：US12177323B2

公开(公告)日：2024-12-24

申请号：US18488551

申请日：2023-10-17

Applicant: Texas Instruments Incorporated

Inventor： Anand G. Dabak ,  Badri N. Varadarajan ,  Il Han Kim ,  Tarkesh Pande

IPC: H04L69/22 ,  H04B3/30 ,  H04B3/54 ,  H04B10/11 ,  H04B1/69

Abstract: Methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described herein provide a preamble design using one or more symbols. One or more preamble symbols may be interspersed within a header portion of a PLC frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise.

公开(公告)号：US20230138448A1

公开(公告)日：2023-05-04

申请号：US18148024

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Anand G. Dabak ,  Badri N Varadarajan ,  Il Han Kim ,  Tarkesh Pande

IPC: H04L69/22 ,  H04B3/30 ,  H04B10/11 ,  H04B3/54

Abstract: Methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described herein provide a preamble design using one or more symbols. One or more preamble symbols may be interspersed within a header portion of a PLC frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise.

公开(公告)号：US20220120596A1

公开(公告)日：2022-04-21

申请号：US17563227

申请日：2021-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amardeep Sathyanarayana ,  David P. Magee ,  Anand G. Dabak ,  Srinath M. Ramaswamy

IPC: G01F1/667 ,  G01S15/10

Abstract: A transducer system with a transducer and circuitry for applying a waveform to excite the transducer during an excitation period. The applying circuitry also comprises circuitry for changing a frequency of the waveform during the excitation period.

公开(公告)号：US11209297B2

公开(公告)日：2021-12-28

申请号：US15236650

申请日：2016-08-15

Applicant: Texas Instruments Incorporated

Inventor： Amardeep Sathyanarayana ,  David P. Magee ,  Anand G. Dabak ,  Srinath M. Ramaswamy

IPC: G01S15/10 ,  G01F1/66

Abstract: A transducer system with a transducer and circuitry for applying a waveform to excite the transducer during an excitation period. The applying circuitry also comprises circuitry for changing a frequency of the waveform during the excitation period.

公开(公告)号：US10236934B2

公开(公告)日：2019-03-19

申请号：US15695983

申请日：2017-09-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tarkesh Pande ,  Anand G. Dabak ,  Il-Han Kim

IPC: H04B3/54

Abstract: Embodiments of the invention provide multiple cyclic prefix lengths for either both the data-payload and frame control header or only the data payload. Frame control header (FCH) and data symbols have an associated cyclic prefix. A table is transmitted in the FCH symbols, which includes a cyclic prefix field to identify the cyclic prefix length used in the data payload. A receiver may know the cyclic prefix length used in the FCH symbols in one embodiment. In other embodiments, the receiver does not know the FCH cyclic prefix length and, therefore, attempts to decode the FCH symbols using different possible cyclic prefix lengths until the FCH symbols are successfully decoded.

公开(公告)号：US20180048354A1

公开(公告)日：2018-02-15

申请号：US15793900

申请日：2017-10-25

Applicant: Texas Instruments Incorporated

Inventor： Il Han Kim ,  Anand G. Dabak ,  Badri N. Varadarajan

IPC: H04B3/54 ,  H04L12/911

CPC classification number: H04B3/542 ,  H04B2203/5408 ,  H04B2203/5416 ,  H04L47/78

Abstract: Systems and methods for application profiles and device classes in power line communications (PLCs) are described. In some embodiments, a PLC device has the device class defined by a PHY layer and may include a processor and a memory coupled to the processor. The memory may be configured to store program instructions, which may be executable by the processor to cause the PLC device to communicate with a higher-level PLC apparatus over a power line using a frequency band. The frequency band may be selected based upon an application profile and/or a device class associated with the PLC device. In some implementations, the higher-level PLC apparatus may include a PLC gateway or a data concentrator, and the PLC device may include a PLC modem or the like. Examples of application profiles include access communications, in-premises connectivity, AC charging, and/or DC charging. Device classes may represent a minimum communication data rate and/or an operating frequency band restriction of the PLC device.

公开(公告)号：US09894189B2

公开(公告)日：2018-02-13

申请号：US15419045

申请日：2017-01-30

Applicant: Texas Instruments Incorporated

Inventor： Gang Xu ,  Ramanuja Vedantham ,  Kumaran Vijayasankar ,  Anand G. Dabak ,  Tarkesh Pande ,  Il Han Kim ,  Xiaolin Lu

IPC: H04J3/24 ,  H04L29/06 ,  H04B3/54

CPC classification number: H04L69/22 ,  H04B3/54 ,  H04B3/542 ,  H04B2203/5408

Abstract: In a disclosed embodiment, a method for communication in a network includes receiving, at a first device registered to the network, a physical layer (PHY) frame that includes a PHY header and a MAC header. The PHY frame may further include a MAC payload. The PHY header includes a destination address field. The method further includes comparing a network address of the first device to the destination address field to determine whether the destination address field stores a value having the same number of bits as the network address. When the comparison indicates that the value stored by the destination address field does not have the same number of bits as the network address, the method skips decoding the MAC header and the MAC payload.

公开(公告)号：US09774535B2

公开(公告)日：2017-09-26

申请号：US15462703

申请日：2017-03-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kumaran Vijayasankar ,  Ramanuja Vedantham ,  Anand G. Dabak ,  Tarkesh Pande ,  Il Han Kim

IPC: H04L12/24 ,  H04L12/801 ,  H04L12/835 ,  H04B3/54

CPC classification number: H04L47/266 ,  H04B3/542 ,  H04B2203/5408 ,  H04L47/12 ,  H04L47/127 ,  H04L47/30 ,  H04L47/32 ,  Y02D50/10

Abstract: A method of powerline communications in a powerline communications (PLC) network including a first node and at least a second node. The first node transmits a data frame to the second node over a PLC channel. The second node has a data buffer for storing received information. The second node runs a flow control algorithm which determines a current congestion condition or a projected congestion condition of the data buffer based on at least one congestion parameter. The current congestion condition and projected congestion condition include nearly congested and fully congested. When the current or projected congestion condition is either nearly congested or fully congested, the second node transmits a BUSY including frame over the PLC channel to at least the first node. The first node defers transmitting of any frames to the second node for a congestion clearing wait time.

公开(公告)号：US09654302B2

公开(公告)日：2017-05-16

申请号：US15192932

申请日：2016-06-24

Applicant: Texas Instruments Incorporated

Inventor： Kumaran Vijayasankar ,  Ramanuja Vedantham ,  Anand G. Dabak

IPC: H04L12/413 ,  H04B3/54 ,  H04L29/06

CPC classification number: H04L12/413 ,  H04B3/54 ,  H04B3/542 ,  H04B2203/5408 ,  H04B2203/5433 ,  H04L69/02

Abstract: Power Line Communications (PLC) device for enhanced carrier sense multiple access (CSMA) protocols are described. The PLC device includes a modem, an AC interface and a PLC engine. The engine is configured for transmitting PLC packets over a plurality of electrical wires using a particular channel. Transmitting a normal priority packet may include attempting to access a communications channel to transmit a frame after a backoff time proportional to a randomly generated number within a contention window (CW), the CW having an initial value carried over from a previous transmission of a different frame. Additionally or alternatively, some of techniques described herein may facilitate the spreading of the time over which devices attempt to transmit packets, thereby reducing the probability of collisions using, for example, Additive Decrease Multiplicative Increase (ADMI) mechanisms.