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    DC Offset Correction with Low Frequency Signal Support Circuits and Methods
    31.
    发明申请
    DC Offset Correction with Low Frequency Signal Support Circuits and Methods 有权
    直流偏移校正与低频信号支持电路和方法

    公开(公告)号：US20150054560A1

    公开(公告)日：2015-02-26

    申请号：US14468009

    申请日：2014-08-25

    Applicant: Texas Instruments Incorporated

    Inventor： Sandeep Kesrimal Oswal ,  Eeshan Miglani ,  H. Mohammed Shuaeb Fazeel ,  Pradeep Nair ,  Anand Hariraj Udupa

    IPC: H03K5/003

    CPC classification number: H03K5/003

    Abstract: DC offset correction is provided with low frequency support. A first input terminal for receiving an input signal is selectively coupled to a resistance and a capacitor that are series coupled between the first input terminal and a corresponding output terminal. In a calibration phase, the series resistance is coupled between the input terminal and the capacitor and an average voltage level of the input is stored on capacitor. In a signal processing phase, the charged capacitor is coupled in series between the input terminal and the output terminal while the resistance is bypassed. The output signal obtained contains the high and low frequency components of the input signal, while the DC offset in the input signal is removed from the output signal. A differential circuit and methods are disclosed. Additional embodiments are disclosed.

    Abstract translation: DC偏移校正提供低频支持。 用于接收输入信号的第一输入端选择性地耦合到串联耦合在第一输入端和相应输出端之间的电阻和电容。 在校准阶段，串联电阻耦合在输入端和电容之间，输入的平均电压电平存储在电容上。 在信号处理阶段，当电阻被旁路时，充电的电容器串联在输入端子和输出端子之间。 获得的输出信号包含输入信号的高频和低频分量，输入信号中的直流偏移从输出信号中去除。 公开了一种差分电路和方法。 公开了另外的实施例。

    Gain mismatch correction for voltage-to-delay preamplifier array
    33.
    发明授权
    Gain mismatch correction for voltage-to-delay preamplifier array 有权

    公开(公告)号：US11438001B2

    公开(公告)日：2022-09-06

    申请号：US17133745

    申请日：2020-12-24

    Applicant: Texas Instruments Incorporated

    Inventor： Narasimhan Rajagopal ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Prasanth K ,  Eeshan Miglani

    IPC: H03M1/34 ,  H03M1/12 ,  H03K5/24 ,  H03L7/081 ,  H03K5/00

    Abstract: A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.

    Piecewise calibration for highly non-linear multi-stage analog-to-digital converter
    36.
    发明授权
    Piecewise calibration for highly non-linear multi-stage analog-to-digital converter 有权

    公开(公告)号：US11316526B1

    公开(公告)日：2022-04-26

    申请号：US17126157

    申请日：2020-12-18

    Applicant: Texas Instruments Incorporated

    Inventor： Narasimhan Rajagopal ,  Visvesvaraya Appala Pentakota ,  Eeshan Miglani

    IPC: H03M1/10 ,  H03M1/16

    Abstract: An analog-to-digital converter includes a voltage-to-delay device, such as a pre-amplifier array, for generating a delay signal based on a first voltage, and delay-based stages for generating digital signals based on the delay signal. In operation, the delay signal is transmitted to a first delay-based stage, or to an intermediate delay-based stage, bypassing the first delay-based stage, to overcome non-linearity of previous stages. If desired, different pre-amplifiers may be used to generate signals for calibration of different delay-based stages. The present disclosure may also involve converting to pseudo-static signals before signals are handed over to a calibration engine, to ease timing and preserve interface area and power. If desired, simple delay elements may be used to correct for non-linearity in a delay-based analog-to-digital converter. The present disclosure may be employed, if desired, in connection with any suitable cascade of non-linear stages.

    Current source noise cancellation
    38.
    发明授权
    Current source noise cancellation 有权

    公开(公告)号：US10389373B2

    公开(公告)日：2019-08-20

    申请号：US16204349

    申请日：2018-11-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jagannathan Venkataraman ,  Eeshan Miglani

    IPC: H03M1/08 ,  H03K17/16 ,  H03M1/74

    Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

    High speed dynamic comparator with common mode stabilization
    39.
    发明授权
    High speed dynamic comparator with common mode stabilization 有权

    公开(公告)号：US10284187B1

    公开(公告)日：2019-05-07

    申请号：US15884813

    申请日：2018-01-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Prasanth K. ,  Jagannathan Venkataraman ,  Eeshan Miglani

    IPC: H03K5/24 ,  H03M1/12 ,  H03M1/46 ,  H03M3/00

    Abstract: A comparator includes a differential input pair of transistors, a pair of cross coupled n-channel metal-oxide-semiconductor field-effect (NMOS) transistors, a pair of p-channel metal-oxide semiconductor field-effect (PMOS) transistors, a first inverter, and a second inverter. The differential input pair of transistors includes a first input transistor and a second input transistor. The pair of cross coupled NMOS transistors includes a first NMOS transistor and a second NMOS transistor. The pair of PMOS transistors includes a first PMOS transistor and a second PMOS transistor. The pair of PMOS transistors are coupled to the pair of cross coupled NMOS transistors. The first inverter is coupled in series with the first PMOS transistor. The second inverter is coupled in series with the second PMOS transistor.

    Current source noise cancellation
    40.
    发明授权
    Current source noise cancellation 有权

    公开(公告)号：US10177775B2

    公开(公告)日：2019-01-08

    申请号：US15927157

    申请日：2018-03-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jagannathan Venkataraman ,  Eeshan Miglani

    IPC: H03M1/06 ,  H03M1/08 ,  H03K17/16 ,  H03M1/74

    Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

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