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公开(公告)号：US11641216B2
公开(公告)日：2023-05-02
申请号：US17689627
申请日：2022-03-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sarma Sundareswara Gunturi , Jagannathan Venkataraman , Jawaharlal Tangudu , Narasimhan Rajagopal , Eeshan Miglani
Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.
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公开(公告)号：US11489515B2
公开(公告)日：2022-11-01
申请号：US17463588
申请日：2021-09-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Eeshan Miglani , Shagun Dusad
Abstract: A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter. The filter includes a notch filter and a bandpass filter.
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公开(公告)号：US11387840B1
公开(公告)日：2022-07-12
申请号：US17129180
申请日：2020-12-21
Applicant: Texas Instruments Incorporated
Abstract: A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.
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公开(公告)号：US09960780B1
公开(公告)日：2018-05-01
申请号：US15649262
申请日：2017-07-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jagannathan Venkataraman , Eeshan Miglani
CPC classification number: H03M1/08 , H03K17/162 , H03K17/165 , H03M1/742
Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.
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公开(公告)号：US09906237B1
公开(公告)日：2018-02-27
申请号：US15582355
申请日：2017-04-28
Applicant: Texas Instruments Incorporated
Inventor： Jagannathan Venkataraman , Eeshan Miglani , Karthikeyan Gunasekaran
CPC classification number: H03M3/436 , H03M1/00 , H03M1/12 , H03M1/747 , H03M3/328 , H03M3/454 , H03M3/50
Abstract: A digital-to-analog converter includes an adder having a plurality of inputs and an output coupled to the output of the converter. The converter further includes a plurality of digital-to-analog (DAC) elements, each DAC element has an output coupled to an input of the adder, and each DAC element has a DAC element input. A plurality of comparators have outputs coupled to a DAC element input. A first input of each comparator is coupled to the input of the converter. A second input of each comparator is selectively coupled to one of a predetermined voltage and a pseudo-random bit sequence (PRBS[n]).
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Patent Agency Ranking
公开(公告)号：US09660665B2
公开(公告)日：2017-05-23
申请号：US15226436
申请日：2016-08-02
Applicant: Texas Instruments Incorporated
Inventor： Eeshan Miglani , Karthikeyan Gunasekaran , Santhosh Kumar Gowdhaman , Shagun Dusad
CPC classification number: H03M3/50 , H03M1/00 , H03M1/001 , H03M1/0626 , H03M1/0665 , H03M1/12 , H03M1/747 , H03M3/30 , H03M3/34 , H03M3/422 , H03M3/458 , H03M7/3004
Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.
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公开(公告)号：US12101096B2
公开(公告)日：2024-09-24
申请号：US17182339
申请日：2021-02-23
Applicant: Texas Instruments Incorporated
Inventor： Prasanth K , Eeshan Miglani , Visvesvaraya Appala Pentakota , Kartik Goel , Jagannathan Venkataraman , Sai Aditya Krishnaswamy Nurani
CPC classification number: H03M1/0612 , H03K5/2481 , H03M1/002 , H03M1/1057
Abstract: A voltage-to-delay converter converts input signals into delay signals, and includes: a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; and a second stage for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltage of the rail-to-rail output signals corresponds to the rail-to-rail voltage. A voltage-to-delay converter block is also described. A circuit for receiving differential input signals, generating corresponding output signals, and removing common mode signals from the output signals is also described.
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公开(公告)号：US20240187013A1
公开(公告)日：2024-06-06
申请号：US18440113
申请日：2024-02-13
Applicant: Texas Instruments Incorporated
Inventor： Himanshu Varshney , Viswanathan Nagarajan , Charls Babu , Narasimhan Rajagopal , Eeshan Miglani , Visvesvaraya A. Pentakota
CPC classification number: H03M1/1009 , H03M1/002 , H03M1/10 , H03M1/12
Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.
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公开(公告)号：US11962318B2
公开(公告)日：2024-04-16
申请号：US17568972
申请日：2022-01-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Himanshu Varshney , Viswanathan Nagarajan , Charls Babu , Narasimhan Rajagopal , Eeshan Miglani , Visvesvaraya A Pentakota
CPC classification number: H03M1/1009 , H03M1/002 , H03M1/10 , H03M1/12
Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.
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公开(公告)号：US09853657B2
公开(公告)日：2017-12-26
申请号：US15489124
申请日：2017-04-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Eeshan Miglani , Karthikeyan Gunasekaran , Santhosh Kumar Gowdhaman , Shagun Dusad
CPC classification number: H03M3/50 , H03M1/00 , H03M1/001 , H03M1/0626 , H03M1/0665 , H03M1/12 , H03M1/747 , H03M3/30 , H03M3/34 , H03M3/422 , H03M3/458 , H03M7/3004
Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.
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