公开(公告)号：US11874718B2

公开(公告)日：2024-01-16

申请号：US17330027

申请日：2021-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Suzanne Mary Vining ,  Bharath Kumar Singareddy ,  Douglas Edward Wente

IPC: G06F1/3215 ,  G06F13/42 ,  G06F13/38 ,  G06F1/3234

CPC classification number: G06F1/3215 ,  G06F1/3253 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0042

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

公开(公告)号：US11843484B2

公开(公告)日：2023-12-12

申请号：US18046716

申请日：2022-10-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suzanne Mary Vining ,  Amit S. Rane ,  Charles Michael Campbell

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03828

Abstract: A system for selecting an equalizer setting of an equalizer to equalize signals received via a communications link. Starting with a first (e.g., minimum) equalizer setting and a threshold voltage near the mid-eye voltage of the equalized output signal, the system estimates the amplitude of the inner eye of the equalized output signal by comparing the equalized output signal to a series of threshold voltages. If the amplitude of the equalized output signal is less than ideal, the system dynamically increases the equalizer setting. The system quickly converges on the equalizer setting for the communication link because, rather than comparing the output signal at every voltage offset using every equalizer setting, the system only evaluates the equalizer settings necessary to select the equalizer setting for the communications link and uses only the voltage offsets necessary to evaluate each equalizer setting.

公开(公告)号：US11762801B2

公开(公告)日：2023-09-19

申请号：US17530669

申请日：2021-11-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Edward Wentroble ,  Suzanne Mary Vining ,  Hassan Omar Ali

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/409 ,  G06F13/4282 ,  G06F2213/0042

Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.

公开(公告)号：US11386036B2

公开(公告)日：2022-07-12

申请号：US16404461

申请日：2019-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Saurabh Goyal ,  Bhupendra Sharma ,  Huanzhang Huang ,  Douglas Edward Wente ,  Suzanne Mary Vining ,  Mustafa Ulvi Erdogan

IPC: G06F13/42 ,  G06F13/38 ,  H04L12/46 ,  H03F3/45 ,  H04B3/58

Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.

公开(公告)号：US20200257354A1

公开(公告)日：2020-08-13

申请号：US16717836

申请日：2019-12-17

Applicant: Texas Instruments Incorporated

Inventor： Suzanne Mary Vining ,  Douglas Edward Wente ,  Win Naing Maung ,  Julie Marie Nirchi

IPC: G06F1/3234 ,  G06F13/42

Abstract: A method includes detecting a micro start of frame packet (μSOF) on a data bus. If there is at least one data packet contained in a microframe during the first threshold period after the μSOF, transmitters are held in an active state. If there is no data packet in the first threshold period after the μSOF, the transmitters are transitioned from the active state to an OFF state. The method also includes transitioning the transmitters from the OFF state to the active state prior to a switchback period before the end of the microframe. The method also includes transitioning the transmitters from the OFF state to the active state if a data packet is received in the OFF state. The method also includes dropping the data packet received in the OFF state and transitioning from the OFF state to the active state when the data packet is dropped.

公开(公告)号：US20200019526A1

公开(公告)日：2020-01-16

申请号：US16033873

申请日：2018-07-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Edward Wentroble ,  Suzanne Mary Vining ,  Hassan Omar Ali

IPC: G06F13/40 ,  G06F13/42

Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.

公开(公告)号：US09710411B2

公开(公告)日：2017-07-18

申请号：US13963264

申请日：2013-08-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Yonghui Tang ,  Suzanne Mary Vining ,  Hao Liu

IPC: G06F13/42 ,  G06F13/38

CPC classification number: G06F13/385

Abstract: A signal conditioner can include a state machine configured to detect a predetermined protocol level mode of a data signal on a bi-directional serial bus. The signal conditioner can also include a re-driver configured to inject current into at least one of a rising edge and a falling edge of the data signal on the bi-directional serial bus in response to the detection of the predetermined protocol level mode.

公开(公告)号：US12253965B2

公开(公告)日：2025-03-18

申请号：US18230797

申请日：2023-08-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Edward Wentroble ,  Suzanne Mary Vining ,  Hassan Omar Ali

IPC: G06F13/40 ,  G06F13/42

Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.

公开(公告)号：US20250021514A1

公开(公告)日：2025-01-16

申请号：US18903010

申请日：2024-10-01

Applicant: Texas Instruments Incorporated

Inventor： Win Naing Maung ,  Suzanne Mary Vining

IPC: G06F13/42 ,  G06F1/3206 ,  G06F13/38

Abstract: A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.

公开(公告)号：US20240396554A1

公开(公告)日：2024-11-28

申请号：US18792708

申请日：2024-08-02

Applicant: Texas Instruments Incorporated

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  G06F13/42 ,  H04B3/36 ,  H04L7/00 ,  H04L25/02

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.