公开(公告)号：US20180350969A1

公开(公告)日：2018-12-06

申请号：US15629885

申请日：2017-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16

Abstract: A semiconductor device is provided, which includes a substrate, a fin structure, a capping layer and an oxide layer. The substrate has a well. The fin structure extends from the well. The capping layer surrounds a top surface and side surfaces of the fin structure. The oxide layer is over the substrate and covers the capping layer. A thickness of a top portion of the oxide layer above the capping layer is greater than a thickness of a sidewall portion of the oxide layer.

公开(公告)号：US20250113602A1

公开(公告)日：2025-04-03

申请号：US18979048

申请日：2024-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei JHAN ,  Chih-Hao WANG ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Kuan-Ting PAN

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate laterally offset from the first semiconductor channel. A first gate structure and a second gate structure are over and laterally surround the first and second semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure. A dielectric feature over the inactive fin includes multiple layers of dielectric material formed through alternating deposition and etching steps.

公开(公告)号：US20240421185A1

公开(公告)日：2024-12-19

申请号：US18786373

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Yi-Ruei JHAN ,  Yen-Ming CHEN ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A device includes a substrate, a first semiconductor fin over the substrate extending in a first lateral direction, a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction, and an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction. A first gate structure surrounds and covers the first semiconductor fin, and extends in a second lateral direction substantially perpendicular to the first lateral direction. A second gate structure surrounds and covers the first vertical stack, and extends in the second lateral direction.

公开(公告)号：US20240194758A1

公开(公告)日：2024-06-13

申请号：US18584862

申请日：2024-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang LIN ,  Kuan-Ting PAN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO ,  Kuo-Cheng CHIANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/78696

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

公开(公告)号：US20230060454A1

公开(公告)日：2023-03-02

申请号：US17463370

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei JHAN ,  Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A device includes a substrate and a fin isolation structure between a first gate structure and a second gate structure. The first gate structure wraps around a first vertical stack of nanostructure channels overlying a first fin. The second gate structure wraps around a second vertical stack of nanostructure channels overlying a second fin. The fin isolation structure extends from an upper surface of the first gate structure to an upper surface of the substrate. A trench isolation structure is between the first fin and the fin isolation structure, and has different etch selectivity than the fin isolation structure.

公开(公告)号：US20220328625A1

公开(公告)日：2022-10-13

申请号：US17480103

申请日：2021-09-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Yi-Ruei JHAN ,  Yen-Ming CHEN ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

Abstract: A device includes a substrate, a first semiconductor fin over the substrate extending in a first lateral direction, a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction, and an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction. A first gate structure surrounds and covers the first semiconductor fin, and extends in a second lateral direction substantially perpendicular to the first lateral direction. A second gate structure surrounds and covers the first vertical stack, and extends in the second lateral direction.

公开(公告)号：US20220093471A1

公开(公告)日：2022-03-24

申请号：US17027282

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Shang-Wen CHANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

公开(公告)号：US20210265508A1

公开(公告)日：2021-08-26

申请号：US16801423

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Huan-Chieh SU ,  Kuan-Ting PAN ,  Shi-Ning JU ,  Chih-Hao WANG

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device structure is provided, which includes a first fin structure over a semiconductor substrate. The first fin structure has multiple first semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a second fin structure over the semiconductor substrate, and the second fin structure has multiple second semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a dielectric fin between the first fin structure and the second fin structure. In addition, the semiconductor device structure includes a metal gate stack wrapping around the first fin structure, the second fin structure, and the dielectric fin. The semiconductor device structure includes a dielectric protection structure over the metal gate stack. The semiconductor device structure also includes an insulating structure penetrating through a bottom surface of the dielectric protection structure and extending into the metal gate stack to be aligned with the dielectric fin.

公开(公告)号：US20210057535A1

公开(公告)日：2021-02-25

申请号：US16547994

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Kuan-Ting PAN ,  Huan-Chieh SU ,  Shi-Ning JU ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a hard mask layer formed over the fin structure. The semiconductor device structure also includes a gate structure formed surrounding the hard mask layer and the fin structure, and a portion of the gate structure is interposed between the fin structure and the hard mask layer. The semiconductor device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure.