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    Chiplets 3D SoIC system integration and fabrication methods
    31.
    发明授权
    Chiplets 3D SoIC system integration and fabrication methods 有权

    公开(公告)号：US11462495B2

    公开(公告)日：2022-10-04

    申请号：US17077618

    申请日：2020-10-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

    IPC: H01L23/00 ,  H01L23/48

    Abstract: A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

    Semiconductor device and manufacturing method thereof
    32.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11139223B2

    公开(公告)日：2021-10-05

    申请号：US16655257

    申请日：2019-10-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Jeng-Nan Hung ,  Kuo-Chung Yee

    IPC: H01L23/34 ,  H01L23/473 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31 ,  H01L21/50 ,  H01L21/308

    Abstract: A semiconductor package includes a semiconductor package, a cap, a seal, and microstructures. The semiconductor package includes at least one semiconductor die. The cap is disposed over an upper surface of the semiconductor package. The seal is located on the semiconductor package and between the cap and the semiconductor package. The cap includes an inflow channel and an outflow channel. The active surface of the at least one semiconductor die faces away from the cap. The cap and an upper surface of the semiconductor package define a circulation recess providing fluidic communication between the inflow channel and the outflow channel. The seal is disposed around the circulation recess. The microstructures are located within the circulation recess, and the microstructures are connected to at least one of the cap and the at least one semiconductor die.

    Package structure and manufacturing method thereof
    34.
    发明授权
    Package structure and manufacturing method thereof 有权

    公开(公告)号：US10971462B2

    公开(公告)日：2021-04-06

    申请号：US16869573

    申请日：2020-05-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

    IPC: H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00 ,  H01Q1/22 ,  H01L21/683 ,  H01Q21/00

    Abstract: A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.

    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    38.
    发明申请
    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200020640A1

    公开(公告)日：2020-01-16

    申请号：US16578403

    申请日：2019-09-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kai-Chiang Wu ,  Chen-Hua Yu ,  Kuo-Chung Yee

    IPC: H01L23/538 ,  H01L23/66 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22

    Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

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