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公开(公告)号：US20230324456A1
公开(公告)日：2023-10-12
申请号：US17877607
申请日：2022-07-29
Applicant: Texas Instruments Incorporated
Inventor： Devanathan Varadarajan , Benjamin Niewenhuis
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/31703 , G01R31/3177
Abstract: An example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor.
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公开(公告)号：US11373726B2
公开(公告)日：2022-06-28
申请号：US16539805
申请日：2019-08-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Devanathan Varadarajan , Varun Singh
Abstract: A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.
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Patent Agency Ranking
公开(公告)号：US20180374556A1
公开(公告)日：2018-12-27
申请号：US15891789
申请日：2018-02-08
Applicant: Texas Instruments Incorporated
Inventor： Devanathan Varadarajan , Sumant Kale
Abstract: In described examples of circuitry and methods for testing multiple memories, a controller generates a sequence of commands to be applied to one or more of the memories, where each given command includes expected data, and a command address. Local adapters are individually coupled with the controller and with an associated memory. Each local adapter translates the command to a memory type of the associated memory, maps the command address to a local address of the associated memory, and provides test results to the controller according to read data from the local address of the associated memory and the expected data of the command.
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公开(公告)号：US09852810B2
公开(公告)日：2017-12-26
申请号：US14733524
申请日：2015-06-08
Applicant: Texas Instruments Incorporated
Inventor： Devanathan Varadarajan , Harsharaj Ellur
CPC classification number: G11C29/4401 , G11C17/16 , G11C17/18 , G11C29/38 , G11C29/785 , G11C29/789 , G11C2029/4402
Abstract: A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register have a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.
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公开(公告)号：US09698779B2
公开(公告)日：2017-07-04
申请号：US14506216
申请日：2014-10-03
Applicant: Texas Instruments Incorporated
Inventor： Devanathan Varadarajan , Karthik Srinivasan , Neel Talakshi Gala
IPC: G06F7/57 , H03K19/00 , H03K19/177
CPC classification number: H03K19/0008 , H03K19/17752 , H03K19/17764
Abstract: Methods for reconfiguring an ASIC at runtime without using voltage over scaling. A functional criticality of a set of logic in the ASIC is identified. Then, the set of logic are classified into a set of regions based on the functional criticality, each region of the set of regions having a target error threshold. Further, each region is power gated at runtime based on the functional criticality such that the target error threshold is achieved without using voltage over scaling.
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公开(公告)号：US20150270016A1
公开(公告)日：2015-09-24
申请号：US14733524
申请日：2015-06-08
Applicant: Texas Instruments Incorporated
Inventor： Devanathan Varadarajan , Harsharaj Ellur
CPC classification number: G11C29/4401 , G11C17/16 , G11C17/18 , G11C29/38 , G11C29/785 , G11C29/789 , G11C2029/4402
Abstract: A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register have a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.
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公开(公告)号：US20150012786A1
公开(公告)日：2015-01-08
申请号：US14038306
申请日：2013-09-26
Applicant: Texas Instruments Incorporated
Inventor： Devanathan Varadarajan , Harsharaj Ellur
IPC: G11C29/12
CPC classification number: G11C29/4401 , G11C17/16 , G11C17/18 , G11C29/38 , G11C29/785 , G11C29/789 , G11C2029/4402
Abstract: A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register have a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.
Abstract translation: 集成电路（IC）中的存储器修复系统，其优化用于存储器修复的熔丝ROM。 IC包括多个存储器包装器。 每个存储器包装器包括具有熔丝寄存器和旁路寄存器的存储器块。 旁路寄存器具有指示多个存储器包装器的有缺陷的存储器包装器的旁路数据。 熔丝ROM控制器耦合到多个存储器包装器。 存储器旁路链将多个存储器封装器中的旁路寄存器与熔丝ROM控制器链接。 fuseROM控制器将旁路数据加载到内存旁路链中。 存储器数据链将多个存储器包装器中的熔丝寄存器与熔丝ROM控制器链接。 存储器数据链被重新配置为响应于加载在存储器旁路链中的旁路数据，将多个存储器包装器中的一组缺陷存储器包装器中的熔丝寄存器链接。
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