公开(公告)号：US09496262B2

公开(公告)日：2016-11-15

申请号：US14572949

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/02 ,  H01L21/70 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/36 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

Abstract translation: 通过形成用于第一极性finFET的第一极性鳍外延层形成包含n沟道finFET和p沟道finFET的集成电路，随后形成暴露第二相反极性鳍片外延区域的硬掩模 层用于第二极性finFET。 在由硬掩模暴露的区域中形成第二极性鳍外延层。 翅片掩模限定第一极性鳍片和第二极性鳍片区域，并且随后的鳍片蚀刻形成相应的鳍片。 隔离介质材料层形成在衬底和鳍片之上。 隔离绝缘材料层被平坦化到鳍片。 隔离电介质材料层是凹进的，使得翅片在隔离介电材料层之上延伸至少10纳米。 栅极电介质层和栅极形成在鳍片上。

公开(公告)号：US09401365B2

公开(公告)日：2016-07-26

申请号：US14559300

申请日：2014-12-03

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra

IPC: H01L29/66 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/265 ,  H01L29/78 ,  H01L29/165 ,  H01L21/266 ,  H01L21/308

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process.

Abstract translation: 通过在两个晶体管的栅极上形成外延隔离层，形成包含相同极性的第一晶体管和第二晶体管的集成电路的工艺，执行外延间隔各向异性蚀刻工艺以在与第一晶体管相邻的垂直表面上形成外延间隔物 晶体管栅极，并从第二晶体管栅极去除外延间隔层，随后执行源极/漏极蚀刻工艺和源极/漏极外延工艺，以在邻近第一和第二栅极的衬底中形成源极/漏极外延区域，使得 第一源极/漏极外延区域与第一栅极与第二栅极与第二栅极与第二栅极/漏极外延区域分离的第二横向空间至少2纳米的横向空间分离。 由所述方法形成的集成电路。

公开(公告)号：US09397182B2

公开(公告)日：2016-07-19

申请号：US14497729

申请日：2014-09-26

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L29/456 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/78 ,  H01L29/7845

Abstract: A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed on the source/drain extension regions and the source/drain regions so that the silicide has a first thickness over the source/drain extension regions and a second thickness over source/drain regions, with the second thickness being greater than the first thickness. Silicide on the source/drain extension regions lowers transistor series resistance which boosts transistor performance and also protects the source/drain extension regions from silicon loss and silicon damage during contact etch.

Abstract translation: 晶体管形成在沟道区域上具有栅极的半导体衬底中，与沟道区相邻的衬底中的源极/漏极延伸区域以及与源极/漏极延伸区域相邻的衬底中的源极/漏极区域。 在源极/漏极延伸区域和源极/漏极区域上形成硅化物，使得硅化物在源极/漏极延伸区域上具有第一厚度，并且在源极/漏极区域上具有第二厚度，其中第二厚度大于第一厚度 厚度。 源极/漏极延伸区上的硅化物降低晶体管串联电阻，从而提高晶体管性能，并且还可以在接触蚀刻期间保护源极/漏极延伸区域免受硅损耗和硅损坏。

公开(公告)号：US09324717B2

公开(公告)日：2016-04-26

申请号：US14573021

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L21/84 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

Abstract translation: 包含n沟道finFET和p沟道finFET的集成电路在硅衬底上具有介电层。 finFET的鳍片具有比硅更高的迁移率的半导体材料。 n沟道finFET的鳍在通过衬底上的电介质层的第一沟槽中的第一硅 - 锗缓冲器上。 p沟道finFET的鳍在通过衬底上的电介质层的第二沟槽中的第二硅 - 锗缓冲器上。 翅片延伸至介电层上方至少10纳米。 散热片通过外延生长在电介质层的沟槽中的硅 - 锗缓冲器上形成，随后CMP平坦化到介电层。 电介质层凹入以暴露翅片。 翅片可以同时或分开地形成。

公开(公告)号：US20150179783A1

公开(公告)日：2015-06-25

申请号：US14635288

申请日：2015-03-02

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Hiroaki Niimi

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L29/78 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.

Abstract translation: 通过沿着形成的侧壁结构的内部形成高k栅极电介质来减小具有金属栅极和高k栅极电介质的MOS晶体管的栅极到源极和栅极到漏极的重叠电容 远离源头和排水沟。

公开(公告)号：US20130214289A1

公开(公告)日：2013-08-22

申请号：US13658785

申请日：2012-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manoj Mehrotra

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: A protective cap is formed on the metal gate of a MOS transistor to protect the metal gate during an etch that forms a source contact opening and a drain contact opening. The protective cap also electrically isolates the source metal contact and the drain metal contact from the metal gate.

Abstract translation: 在MOS晶体管的金属栅极上形成保护帽，以在形成源极接触开口和漏极接触开口的蚀刻期间保护金属栅极。 保护盖还将源极金属触点和漏极金属触点与金属栅极电隔离。