公开(公告)号：US10026839B2

公开(公告)日：2018-07-17

申请号：US15191696

申请日：2016-06-24

申请人： Texas Instruments Incorporated

发明人： Manoj Mehrotra

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L27/11 ,  H01L29/66 ,  H01L27/092 ,  H01L21/265 ,  H01L29/165 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L21/266 ,  H01L21/308

摘要： A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process.

公开(公告)号：US20150187770A1

公开(公告)日：2015-07-02

申请号：US14572949

申请日：2014-12-17

申请人： Texas Instruments Incorporated

发明人： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

摘要： An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

摘要翻译： 通过形成用于第一极性finFET的第一极性鳍外延层形成包含n沟道鳍FETFET和p沟道finFET的集成电路，随后形成暴露第二相反极性鳍片外延区域的硬掩模 层用于第二极性finFET。 在由硬掩模暴露的区域中形成第二极性鳍外延层。 翅片掩模限定第一极性鳍片和第二极性鳍片区域，并且随后的鳍片蚀刻形成相应的鳍片。 隔离介质材料层形成在衬底和鳍片之上。 隔离绝缘材料层被平坦化到鳍片。 隔离介电材料层是凹进的，使得翅片在隔离介电材料层之上延伸至少10纳米。 栅极电介质层和栅极形成在鳍片上。

公开(公告)号：US20140175597A1

公开(公告)日：2014-06-26

申请号：US14190229

申请日：2014-02-26

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Manoj Mehrotra

IPC分类号： H01L29/06

CPC分类号： H01L29/0649 ,  H01L21/3086 ,  H01L21/76232

摘要： An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of the isolation trench, forming polysilicon sidewalls on the first shallow portion, and then etching the second deeper portion.

摘要翻译： 半导体器件的衬底中的隔离沟槽包括第一浅部，过渡区和第二较深部。 隔离沟槽包含介电填料。 隔离沟槽通过首先形成隔离沟槽的第一浅部，在第一浅部上形成多晶硅侧壁，然后蚀刻第二较深部分而形成。

公开(公告)号：US20140124874A1

公开(公告)日：2014-05-08

申请号：US13671730

申请日：2012-11-08

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Manoj Mehrotra ,  Hiroaki Niimi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.

摘要翻译： 通过沿着形成的侧壁结构的内部形成高k栅极电介质来减小具有金属栅极和高k栅极电介质的MOS晶体管的栅极到源极和栅极到漏极的重叠电容 远离源头和排水沟。

公开(公告)号：US20240363434A1

公开(公告)日：2024-10-31

申请号：US18308785

申请日：2023-04-28

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Manoj Mehrotra

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7848

摘要： Transistors with raised source/drain structures and methods of making the transistors are described. A method for making such transistors includes forming a first gate and a second gate on a substrate, forming a p-doped region adjacent the first gate, and forming an n-doped region adjacent the second gate. The method further includes forming a silicon germanium (SiGe) region in a portion of the p-doped region. Subsequently, the method simultaneously forms raised source-drain structures over the SiGe region and on the n-doped region.

公开(公告)号：US11417646B2

公开(公告)日：2022-08-16

申请号：US15172559

申请日：2016-06-03

申请人： Texas Instruments Incorporated

发明人： Manoj Mehrotra ,  Terry J. Bordelon ,  Deborah J. Riley

IPC分类号： H01L27/092 ,  H01L27/06 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/417 ,  H01L21/265 ,  H01L29/78 ,  H01L29/165 ,  H01L29/737 ,  H01L23/535 ,  H01L29/10 ,  H01L29/161

摘要： An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.

公开(公告)号：US10978353B2

公开(公告)日：2021-04-13

申请号：US16206045

申请日：2018-11-30

申请人： Texas Instruments Incorporated

发明人： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/161

摘要： An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

公开(公告)号：US20170033018A1

公开(公告)日：2017-02-02

申请号：US15292373

申请日：2016-10-13

申请人： Texas Instruments Incorporated

发明人： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L21/02 ,  H01L29/10

CPC分类号： H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

摘要： An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

摘要翻译： 通过形成用于第一极性finFET的第一极性鳍外延层形成包含n沟道鳍FETFET和p沟道finFET的集成电路，随后形成暴露第二相反极性鳍片外延区域的硬掩模 层用于第二极性finFET。 在由硬掩模暴露的区域中形成第二极性鳍外延层。 翅片掩模限定第一极性鳍片和第二极性鳍片区域，并且随后的鳍片蚀刻形成相应的鳍片。 隔离介质材料层形成在衬底和鳍片之上。 隔离绝缘材料层被平坦化到鳍片。 隔离介电材料层是凹进的，使得翅片在隔离介电材料层之上延伸至少10纳米。 栅极电介质层和栅极形成在鳍片上。

公开(公告)号：US20150187771A1

公开(公告)日：2015-07-02

申请号：US14578732

申请日：2014-12-22

申请人： Texas Instruments Incorporated

发明人： Hiroaki Niimi ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC分类号： H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/28 ,  H01L21/321 ,  H01L29/51 ,  H01L21/027

CPC分类号： H01L27/092 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

摘要翻译： 一种具有金属栅极NMOS晶体管的集成电路和方法，其在高质量热生长界面电介质上具有高k第一栅极电介质，并且具有在化学生长界面电介质上具有高k最后栅极电介质的金属栅极PMOS晶体管。

公开(公告)号：US09000539B2

公开(公告)日：2015-04-07

申请号：US13671730

申请日：2012-11-08

申请人： Texas Instruments Incorporated

发明人： Manoj Mehrotra ,  Hiroaki Niimi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/78 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.

摘要翻译： 通过沿着形成的侧壁结构的内部形成高k栅极电介质来减小具有金属栅极和高k栅极电介质的MOS晶体管的栅极到源极和栅极到漏极的重叠电容 远离源头和排水沟。