公开(公告)号：US20120151748A1

公开(公告)日：2012-06-21

申请号：US13404485

申请日：2012-02-24

申请人： Mete Erturk ,  John D. Gillis ,  Casey J. Grant ,  David Scagnelli ,  Anthony K. Stamper

发明人： Mete Erturk ,  John D. Gillis ,  Casey J. Grant ,  David Scagnelli ,  Anthony K. Stamper

IPC分类号： G01R31/28 ,  G06F17/50

CPC分类号： H01F17/0006 ,  H01F17/04 ,  H01F27/2847 ,  H01F41/04 ,  H01F41/041 ,  H01F41/045 ,  H01F2017/0053 ,  H01F2017/0073 ,  H01F2017/046 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49004 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49073 ,  Y10T29/49156 ,  H01L2924/00

摘要： Embodiments disclosed include methods of designing an inductor. The inductor can include a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line.

摘要翻译： 公开的实施例包括设计电感器的方法。 电感器可以包括包括至少一个匝的导电线和位于导电线的区域的内部内的开口。

公开(公告)号：US07851923B2

公开(公告)日：2010-12-14

申请号：US12410728

申请日：2009-03-25

申请人： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

发明人： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

摘要翻译： 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

公开(公告)号：US20100237468A1

公开(公告)日：2010-09-23

申请号：US12552317

申请日：2009-09-02

申请人： Douglas M. Daley ,  Mete Erturk ,  Edward J. Gordon

发明人： Douglas M. Daley ,  Mete Erturk ,  Edward J. Gordon

IPC分类号： H01L29/93 ,  G06F17/50 ,  H01L21/329

CPC分类号： H01G7/00 ,  G06F17/5054 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： On-chip capacitors with a variable capacitance, as well as design structures for a radio frequency integrated circuit, and method of fabricating and method of tuning on-chip capacitors. The on-chip capacitor includes first and second ports powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. Each of the first and second voltage-controlled units is switched between a first state in which the first and second electrodes are electrically isolated from the first and second ports and a second state. When the first voltage-controlled unit is switched to the second state, the first electrode is electrically connected with the first port. When the second voltage-controlled unit is switched to the second state the second electrode is electrically connected with the second port. The on-chip capacitor has a larger capacitance value when the first and second voltage-controlled units are in the second state.

摘要翻译： 具有可变电容的片上电容器，以及用于射频集成电路的设计结构，以及制造方法和片上电容器的调谐方法。 片上电容器包括由相反极性供电的第一和第二端口，第一和第二电极以及第一和第二电压控制单元。 第一和第二压控单元中的每一个在第一和第二电极与第一和第二端口电隔离的第一状态和第二状态之间切换。 当第一电压控制单元切换到第二状态时，第一电极与第一端口电连接。 当第二电压控制单元切换到第二状态时，第二电极与第二端口电连接。 当第一和第二电压控制单元处于第二状态时，片上电容器具有较大的电容值。

公开(公告)号：US07659598B2

公开(公告)日：2010-02-09

申请号：US12371662

申请日：2009-02-16

申请人： Mete Erturk ,  Alvin J. Joseph ,  Anthony K. Stamper

发明人： Mete Erturk ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC分类号： H01L29/70

CPC分类号： H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisions are made to prevent diffusion of copper (Cu) when that is used as the metal in the cheese metal of the ground shield. The ground shield provides a low resistance, very thick metal at a first metal (M1) level for passive RF elements in conjunction with the standard back-end-of-line (BEOL) integration. The invention also includes a method of forming the ground shield.

摘要翻译： 公开了一种接地屏蔽，其包括位于电介质层内的“干酪”金属和位于干酪金属上的第一金属层内的金属区域。 接地屏蔽可以根据所使用的金属具有不同的形式，并且当用作接地屏蔽的奶酪金属中的金属时，设置防止铜（Cu）的扩散。 接地屏蔽为第一金属（M1）级别提供低电阻，非常厚的金属，用于与标准后端（BEOL）集成结合的无源RF元件。 本发明还包括形成接地屏蔽的方法。

公开(公告)号：US07563714B2

公开(公告)日：2009-07-21

申请号：US11275542

申请日：2006-01-13

申请人： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

发明人： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter Of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

摘要翻译： 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介质隔离的周边内对准并且延伸到所述电介质隔离; 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

公开(公告)号：US20070190692A1

公开(公告)日：2007-08-16

申请号：US11275542

申请日：2006-01-13

申请人： Mete Erturk ,  Robert Groves ,  Jeffrey Johnson ,  Alvin Joseph ,  Qizhi Liu ,  Edmund Sprogis ,  Anthony Stamper

发明人： Mete Erturk ,  Robert Groves ,  Jeffrey Johnson ,  Alvin Joseph ,  Qizhi Liu ,  Edmund Sprogis ,  Anthony Stamper

IPC分类号： H01L21/50

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

摘要翻译： 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔离; 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。