公开(公告)号：US07678696B2

公开(公告)日：2010-03-16

申请号：US12188230

申请日：2008-08-08

Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

IPC: H01L21/44

CPC classification number: H01L21/76898

Abstract: A method of making a through wafer via. The method includes: forming a trench in a semiconductor substrate, the trench open to a top surface of the substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; oxidizing the polysilicon layer to convert the polysilicon layer to a silicon oxide layer on the sidewalls and bottom of the trench, the silicon oxide layer not filling the trench; filling remaining space in the trench with an electrical conductor; and thinning the substrate from a bottom surface of the substrate and removing the silicon oxide layer from the bottom of the trench. The method may further include forming a metal layer on the silicon oxide layer before filling the trench.

Abstract translation: 制造通过晶片通孔的方法。 该方法包括：在半导体衬底中形成沟槽，沟槽通向衬底的顶表面; 在沟槽的侧壁和底部上形成多晶硅层; 氧化多晶硅层以将多晶硅层转变成沟槽的侧壁和底部上的氧化硅层，氧化硅层不填充沟槽; 用电导体填充沟槽中的剩余空间; 以及从衬底的底表面使衬底细化并从沟槽的底部去除氧化硅层。 该方法还可以包括在填充沟槽之前在氧化硅层上形成金属层。

公开(公告)号：US20080261122A1

公开(公告)日：2008-10-23

申请号：US11738070

申请日：2007-04-20

Applicant: Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

Inventor： Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

IPC: G03C5/00 ,  G03F1/00

CPC classification number: G03F1/30 ,  G03F1/48 ,  G03F1/54

Abstract: A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and a top surface; the non-printable region comprising a second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and a top surface; and a capping layer on the sidewalls of the first opaque regions and the sidewalls of the second opaque region.

Abstract translation: 光掩模和制造光掩模的方法。 所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和顶表面; 所述不可打印区域包括在所述基板的顶表面上方升高的第二不透明区域，所述第二不透明区域具有侧壁和顶表面; 以及在第一不透明区域的侧壁和第二不透明区域的侧壁上的覆盖层。

公开(公告)号：US06294406B1

公开(公告)日：2001-09-25

申请号：US09350274

申请日：1999-07-06

Applicant: Claude Louis Bertin ,  Thomas George Ference ,  Wayne John Howell ,  Edmund Juris Sprogis

Inventor： Claude Louis Bertin ,  Thomas George Ference ,  Wayne John Howell ,  Edmund Juris Sprogis

IPC: H01L2144

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81

Abstract: The advantages of the invention are realized by a chip-on-chip module having at least two fully functional chips, electrically connected together, and a chip-on-chip component connection/interconnection for electrically connecting the fully functional chips to external circuitry.

Abstract translation: 本发明的优点通过具有至少两个完全功能的芯片，电连接在一起的片上芯片模块和用于将全功能芯片电连接到外部电路的片上芯片组件连接/互连来实现。

公开(公告)号：US5923181A

公开(公告)日：1999-07-13

申请号：US840041

申请日：1997-04-24

Applicant: Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

Inventor： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

IPC: G01R31/26 ,  G01R1/04 ,  G01R31/28 ,  H01L21/66 ,  H01L25/00 ,  G01R31/02

CPC classification number: G01R31/2863 ,  G01R1/0483 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2889 ,  H01L2924/0002

Abstract: Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.

Abstract translation: 阐述了以堆叠配置层叠在一起的多个半导体器件芯片的老化应力和同时测试方法和装置，以限定多芯片模块。 通过将临时互连线连接到多芯片模块的访问表面来实现测试。 该临时互连布线使模块内的至少一些半导体器件芯片电互连。 在老化应力和测试之前，会发生单独的电气筛选步骤，以识别临时互连线路和多芯片模块之间的连接中的任何电气缺陷。 如果识别出电气缺陷，则提出了用于去除或隔离缺陷的各种技术。 此后，使用临时互连线路进行多芯片模块内的半导体芯片的老化强度和同时测试。 描述了各种对准和测试夹具，以便于该多芯片模块内的半导体芯片的老化和同时测试。

公开(公告)号：US08637937B2

公开(公告)日：2014-01-28

申请号：US13364804

申请日：2012-02-02

Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/19 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.

Abstract translation: 一种硅通孔结构和一种制造通硅通孔的方法。 该方法包括：（a）在硅衬底中形成沟槽，沟槽通向衬底的顶表面; （b）在所述沟槽的侧壁上形成二氧化硅层，所述二氧化硅层不填充所述沟槽; （c）用多晶硅填充沟槽中的剩余空间; （c）之后，（d）在衬底中制造至少一部分CMOS器件; （e）从所述沟槽去除所述多晶硅，所述电介质层残留在所述沟槽的侧壁上; （f）用导电芯重新填充沟槽; 在（f）之后，（g）在衬底的顶表面上形成一个或多个布线层，与接触导电芯的顶表面的最接近衬底的一个或多个布线层的布线层的布线。

公开(公告)号：US07741722B2

公开(公告)日：2010-06-22

申请号：US11690181

申请日：2007-03-23

Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

Abstract translation: 一种晶片通孔结构及其形成方法。 贯通晶片通孔结构包括具有开口和顶部晶片表面的晶片。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 贯通晶片通孔结构还包括在开口中的通晶片通孔。 贯通晶片通孔具有矩形板的形状。 贯通晶片通孔在第一参考方向上的高度基本上等于晶片在第一参考方向上的厚度。 贯穿晶片通孔在第二参考方向上的长度比通过晶片通孔在第三参考方向上的宽度大至少十倍。 第一，第二和第三参考方向彼此垂直。

公开(公告)号：US20100032764A1

公开(公告)日：2010-02-11

申请号：US12188228

申请日：2008-08-08

Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

IPC: H01L27/08 ,  H01L21/76

CPC classification number: H01L24/19 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core.

Abstract translation: 一种硅通孔结构和一种制造通硅通孔的方法。 该方法包括：（a）在硅衬底中形成沟槽，沟槽通向衬底的顶表面; （b）在所述沟槽的侧壁上形成二氧化硅层，所述二氧化硅层不填充所述沟槽; （c）用多晶硅填充沟槽中的剩余空间; （c）之后，（d）在衬底中制造至少一部分CMOS器件; （e）从所述沟槽去除所述多晶硅，所述电介质层残留在所述沟槽的侧壁上; （f）用导电芯重新填充沟槽; 在（f）之后，（g）在衬底的顶表面上形成一个或多个布线层，所述一个或多个布线层的布线层的布线层接触到所述导电芯的顶表面。

公开(公告)号：US20080274583A1

公开(公告)日：2008-11-06

申请号：US11690181

申请日：2007-03-23

Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

IPC: H01L21/00

CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

Abstract translation: 一种晶片通孔结构及其形成方法。 贯通晶片通孔结构包括具有开口和顶部晶片表面的晶片。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 贯通晶片通孔结构还包括在开口中的通晶片通孔。 贯通晶片通孔具有矩形板的形状。 贯通晶片通孔在第一参考方向上的高度基本上等于晶片在第一参考方向上的厚度。 贯穿晶片通孔在第二参考方向上的长度比通过晶片通孔在第三参考方向上的宽度大至少十倍。 第一，第二和第三参考方向彼此垂直。

公开(公告)号：US06642080B1

公开(公告)日：2003-11-04

申请号：US09691546

申请日：2000-10-18

Applicant: Thomas George Ference ,  Wayne John Howell ,  Edmund Juris Sprogis

Inventor： Thomas George Ference ,  Wayne John Howell ,  Edmund Juris Sprogis

IPC: H01L2144

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2224/29099 ,  H01L2924/00

Abstract: Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (e.g., a second height greater than the first height). The first and second characteristics of the chip-on-chip interconnections allow for chip-on-chip connections to other packages, substrates or chips of different levels and/or compositions.

Abstract translation: 公开了各种特性的片上芯片互连，例如直径，高度和/或组成的变化。 在接合平面上的第一芯片上芯片互连具有第一特性（例如，第一高度），并且在同一接合平面上的第二芯片上芯片互连具有第二特性（例如，第二高度大于 第一高度）。 片上芯片互连的第一和第二特性允许片上芯片连接到其他封装，基板或不同级别和/或组成的芯片。

公开(公告)号：US06507115B2

公开(公告)日：2003-01-14

申请号：US09736584

申请日：2000-12-14

Applicant: Harm Peter Hofstee ,  Robert Kevin Montoye ,  Edmund Juris Sprogis

Inventor： Harm Peter Hofstee ,  Robert Kevin Montoye ,  Edmund Juris Sprogis

IPC: H01L2348

CPC classification number: H01L23/4334 ,  H01L23/3677 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package. Low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are connectable to externally supplied power signals. The power signals provided to the signals posts are routed to circuits within the second set of die over relatively short metallization interconnects. The signal posts may be connected to thermally conductive via elements and the package may include heat spreaders on upper and lower package surfaces. The first die may comprise a DRAM while the second set of die comprise portions of a general purpose microprocessor. The power signals provided to the second set of die may be connected to a capacitor terminal in the first die to provide power signal decoupling.