公开(公告)号：US07045855B2

公开(公告)日：2006-05-16

申请号：US10777207

申请日：2004-02-13

申请人： Björn Fischer ,  Matthias Goldbach ,  Stefan Jakschik ,  Till Schlösser

发明人： Björn Fischer ,  Matthias Goldbach ,  Stefan Jakschik ,  Till Schlösser

IPC分类号： H01L29/792

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/31612 ,  H01L21/31616 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10838 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L28/56 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/785

摘要： A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first dielectric constant, which is situated directly above the channel region, and an overlying second gate dielectric made of a second material having a second thickness and a second dielectric constant, which is significantly greater than the first dielectric constant; and the first thickness of the first gate dielectric and the second thickness of the second gate dielectric being chosen such that the corresponding thickness of a gate structure with the first gate dielectric, to obtain the same threshold voltage, is at least of the same magnitude as a thickness equal to the sum of the first thickness and the second thickness. The invention also relates to a corresponding fabrication method.

摘要翻译： 具有栅极结构的半导体器件，所述栅极结构具有由第一材料制成的第一栅极电介质，所述第一材料具有位于所述沟道区域正上方的第一厚度和第一介电常数，以及由第二栅极电介质构成的覆盖的第二栅极电介质 材料具有明显大于第一介电常数的第二厚度和第二介电常数; 并且第一栅极电介质的第一厚度和第二栅极电介质的第二厚度被选择为使得具有第一栅极电介质的栅极结构的相应厚度以获得相同的阈值电压至少与 厚度等于第一厚度和第二厚度之和的厚度。 本发明还涉及相应的制造方法。

公开(公告)号：US08445963B2

公开(公告)日：2013-05-21

申请号：US12950977

申请日：2010-11-19

申请人： Stefan Jakschik ,  Nadine Collaert

发明人： Stefan Jakschik ,  Nadine Collaert

IPC分类号： H01L27/12

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/66787 ,  H01L29/78684

摘要： A multi-gate device is disclosed. In one aspect, the device includes a substrate having a first semiconductor layer of a first carrier mobility enhancing parameter, a buried insulating layer, and a second semiconductor layer with a second carrier mobility enhancing parameter. The device also includes a first active region electrically isolated from a second active region in the substrate. The first active region has a first fin grown on the first semiconductor layer and having the first mobility enhancing parameter. The second active region has a second fin grown on the second semiconductor layer and having the second mobility enhancing parameter. The device also includes a dielectric layer over the second semiconductor layer which is located between the first fin and the second fin. The first and second fins protrude through and above the dielectric layer.

摘要翻译： 公开了一种多栅极器件。 一方面，该器件包括具有第一载流子迁移率增强参数的第一半导体层，掩埋绝缘层和具有第二载流子迁移率增强参数的第二半导体层的衬底。 该器件还包括与衬底中的第二有源区电隔离的第一有源区。 第一有源区具有在第一半导体层上生长并具有第一迁移率增强参数的第一鳍。 第二有源区具有在第二半导体层上生长并具有第二迁移率增强参数的第二鳍。 该器件还包括位于第一鳍片和第二鳍片之间的位于第二半导体层上的电介质层。 第一和第二散热片突出穿过介电层的上方。

公开(公告)号：US20110068375A1

公开(公告)日：2011-03-24

申请号：US12950977

申请日：2010-11-19

申请人： Stefan Jakschik ,  Nadine Collaert

发明人： Stefan Jakschik ,  Nadine Collaert

IPC分类号： H01L29/78

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/66787 ,  H01L29/78684

摘要： A multi-gate device is disclosed. In one aspect, the device includes a substrate having a first semiconductor layer of a first carrier mobility enhancing parameter, a buried insulating layer, and a second semiconductor layer with a second carrier mobility enhancing parameter. The device also includes a first active region electrically isolated from a second active region in the substrate. The first active region has a first fin grown on the first semiconductor layer and having the first mobility enhancing parameter. The second active region has a second fin grown on the second semiconductor layer and having the second mobility enhancing parameter. The device also includes a dielectric layer over the second semiconductor layer which is located between the first fin and the second fin. The first and second fins protrude through and above the dielectric layer.

摘要翻译： 公开了一种多栅极器件。 一方面，该器件包括具有第一载流子迁移率增强参数的第一半导体层，掩埋绝缘层和具有第二载流子迁移率增强参数的第二半导体层的衬底。 该器件还包括与衬底中的第二有源区电隔离的第一有源区。 第一有源区具有在第一半导体层上生长并具有第一迁移率增强参数的第一鳍。 第二有源区具有在第二半导体层上生长并具有第二迁移率增强参数的第二鳍。 该器件还包括位于第一鳍片和第二鳍片之间的位于第二半导体层上的电介质层。 第一和第二散热片突出穿过介电层的上方。

公开(公告)号：US07842559B2

公开(公告)日：2010-11-30

申请号：US12340302

申请日：2008-12-19

申请人： Stefan Jakschik ,  Nadine Collaert

发明人： Stefan Jakschik ,  Nadine Collaert

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/66787 ,  H01L29/78684

摘要： A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter.

摘要翻译： 公开了一种制造多栅极器件的方法。 一方面，该方法包括提供具有第一载流子迁移率增强参数的第一半导体层的衬底，绝缘层，具有与第一载流子迁移率增强参数不同的第二载流子迁移率增强参数的第二半导体层。 然后在基板上提供第一和第二电介质层。 第一沟槽通过介电层，第二半导体层和掩埋绝缘层形成在第一有源区中。 第一鳍形成在第一沟槽中，突出在第一介电层上方并具有第一载流子迁移率增强参数。 第二沟槽通过介电层形成在第二有源区中。 第二鳍形成在第二沟槽中，突出在第一介电层上方并具有第二迁移率增强参数。

公开(公告)号：US20090159972A1

公开(公告)日：2009-06-25

申请号：US12340302

申请日：2008-12-19

申请人： Stefan Jakschik ,  Nadine Collaert

发明人： Stefan Jakschik ,  Nadine Collaert

IPC分类号： H01L27/12 ,  H01L21/20

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/66787 ,  H01L29/78684

摘要： A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter.

摘要翻译： 公开了一种制造多栅极器件的方法。 一方面，该方法包括提供具有第一载流子迁移率增强参数的第一半导体层的衬底，绝缘层，具有与第一载流子迁移率增强参数不同的第二载流子迁移率增强参数的第二半导体层。 然后在基板上提供第一和第二电介质层。 第一沟槽通过介电层，第二半导体层和掩埋绝缘层形成在第一有源区中。 第一鳍形成在第一沟槽中，突出在第一介电层上方并具有第一载流子迁移率增强参数。 第二沟槽通过介电层形成在第二有源区中。 第二鳍形成在第二沟槽中，突出在第一介电层上方并具有第二迁移率增强参数。

公开(公告)号：US20100110753A1

公开(公告)日：2010-05-06

申请号：US12262830

申请日：2008-10-31

申请人： Stefan Slesazeck ,  Rolf Weis ,  Stefan Jakschik

发明人： Stefan Slesazeck ,  Rolf Weis ,  Stefan Jakschik

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C11/34 ,  H01L21/20

CPC分类号： H01L27/1159 ,  G11C5/063 ,  G11C11/22 ,  G11C11/223 ,  H01L27/0207 ,  H01L27/11592 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

摘要： An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lines electrically coupled to first load regions of a load path of the switching devices and a word line electrically coupled to gate electrodes of the switching devices. The address circuit is configured to control a write cycle such that a first voltage is induced at the gate dielectrics of selected ones of the switching devices and a second voltage is induced at the gate dielectrics of non-selected ones of the switching devices. The first voltage suffices to switch the gate dielectrics of the selected devices from the first to the second polarization state and the second voltage does not suffice to switch the gate dielectrics of the non-selected devices.

摘要翻译： 集成电路包括多个开关器件，其中每个器件包括能够承受至少第一和第二极化状态的栅极电介质。 集成电路还包括地址电路，其被配置为控制电耦合到开关器件的负载路径的第一负载区域的位线和与开关器件的栅极电耦合的字线。 地址电路被配置为控制写入周期，使得在所选择的开关器件的栅极电介质处感应出第一电压，并且在非选择的开关器件的栅极电介质处感应出第二电压。 第一电压足以将所选择的器件的栅极电介质从第一极化状态切换到第二极化状态，并且第二电压不足以切换未选择器件的栅极电介质。

公开(公告)号：US20080296680A1

公开(公告)日：2008-12-04

申请号：US11755137

申请日：2007-05-30

申请人： Matthias Goldbach ,  Stefan Jakschik

发明人： Matthias Goldbach ,  Stefan Jakschik

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/425

CPC分类号： H01L21/823437 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

摘要： A method of making an integrated circuit including doping a fin is disclosed. The method includes providing a substrate having at least one fin of a semiconductor material and carrying out a gas-phase doping of the at least one fin.

摘要翻译： 公开了一种制造包括掺杂鳍片的集成电路的方法。 该方法包括提供具有半导体材料的至少一个翅片并执行至少一个翅片的气相掺杂的基底。