公开(公告)号：US08722500B2

公开(公告)日：2014-05-13

申请号：US13237688

申请日：2011-09-20

申请人： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

发明人： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/76897

摘要： Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.

摘要翻译： 提供了用于制造包括门到活动触点的集成电路的方法。 一种方法包括在替代栅极技术中处理IC，包括在虚拟栅极上形成伪栅极，侧壁间隔物以及金属硅化物触点到有源区域。 填充层被平坦化以暴露伪栅极并且去除虚拟栅极。 形成掩模，其具有覆盖通道区域的从其去除虚拟栅极的一部分的开口和相邻的金属硅化物接触的一部分。 蚀刻填充层和暴露在掩模开口中的侧壁间隔部分，以露出相邻的金属硅化物接触部分。 沉积覆盖沟道区域和暴露的金属硅化物接触的栅电极材料，并被平坦化以形成栅电极和栅极与金属的硅化物接触互连。

公开(公告)号：US20120196425A1

公开(公告)日：2012-08-02

申请号：US13354613

申请日：2012-01-20

申请人： Thilo Scheiper ,  Andy Wei ,  Stefan Flachowsky ,  Jan Hoentschel

发明人： Thilo Scheiper ,  Andy Wei ,  Stefan Flachowsky ,  Jan Hoentschel

IPC分类号： H01L21/762 ,  H01L21/28

CPC分类号： H01L29/785 ,  H01L21/823828 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66795

摘要： When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, superior process uniformity may be achieved by implementing at least one planarization process after the deposition of the placeholder material, such as the polysilicon material, and prior to actually patterning the gate electrode structures.

摘要翻译： 当基于替代栅极方法形成复杂的高k金属栅电极结构时，可以通过在诸如多晶硅材料的占位符材料的沉积之后实施至少一个平坦化工艺，并且在实际上 图案化栅电极结构。

公开(公告)号：US20100301416A1

公开(公告)日：2010-12-02

申请号：US12784819

申请日：2010-05-21

申请人： Jan Hoentschel ,  Stefan Flachowsky ,  Andy Wei

发明人： Jan Hoentschel ,  Stefan Flachowsky ,  Andy Wei

IPC分类号： H01L27/12 ,  H01L21/782

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7846

摘要： In advanced SOI devices, a high tensile strain component may be achieved on the basis of a globally strained semiconductor layer, while at the same time a certain compressive strain may be induced in P-channel transistors by appropriately selecting a height-to-length aspect ratio of the corresponding active regions. It has been recognized that the finally obtained strain distribution in the active regions is strongly dependent on the aspect ratio of the active regions. Thus, by selecting a moderately low height-to-length aspect ratio for N-channel transistors, a significant fraction of the initial tensile strain component may be preserved. On the other hand, a moderately high height-to-length aspect ratio for the P-channel transistor may result in a compressive strain component in a central surface region of the active region.

摘要翻译： 在先进的SOI器件中，可以在全局应变半导体层的基础上实现高拉伸应变分量，同时通过适当地选择高度 - 长度方面，可以在P沟道晶体管中产生一定的压缩应变 相应活性区的比例。 已经认识到，有效区域中最终获得的应变分布强烈地取决于有源区的纵横比。 因此，通过为N沟道晶体管选择中等的高度 - 长度长宽比，可以保留初始拉伸应变分量的很大一部分。 另一方面，用于P沟道晶体管的中等高度的长宽比可能导致有源区的中心表面区域中的压缩应变分量。

公开(公告)号：US08698243B2

公开(公告)日：2014-04-15

申请号：US13953349

申请日：2013-07-29

申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/26586 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.

摘要翻译： 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。

公开(公告)号：US20140042550A1

公开(公告)日：2014-02-13

申请号：US13572343

申请日：2012-08-10

申请人： Stefan Flachowsky ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Jan Hoentschel

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823418 ,  H01L21/823468

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes simultaneously shielding a shielded region of a semiconductor substrate and exposing a surface of the shielded region of the semiconductor substrate. An ion implantation is performed to form implant areas in a non-shielded region of the semiconductor substrate adjacent the shielded region. Also, the semiconductor substrate is silicided to form a silicided area in the shielded region of the semiconductor substrate.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括同时屏蔽半导体衬底的屏蔽区域并暴露半导体衬底的屏蔽区域的表面。 执行离子注入以在与屏蔽区域相邻的半导体衬底的非屏蔽区域中形成注入区域。 此外，半导体衬底被硅化以在半导体衬底的屏蔽区域中形成硅化区域。

公开(公告)号：US20130320449A1

公开(公告)日：2013-12-05

申请号：US13482393

申请日：2012-05-29

申请人： Jan Hoentschel ,  Shiang Yang Ong ,  Stefan Flachowsky ,  Thilo Scheiper

发明人： Jan Hoentschel ,  Shiang Yang Ong ,  Stefan Flachowsky ,  Thilo Scheiper

IPC分类号： H01L21/8238 ,  H01L27/088 ,  H01L21/336

CPC分类号： H01L27/0922 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/458 ,  H01L29/4925 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.

公开(公告)号：US08586440B2

公开(公告)日：2013-11-19

申请号：US13192332

申请日：2011-07-27

申请人： Stefan Flachowsky ,  Steven Langdon ,  Thomas Feudel

发明人： Stefan Flachowsky ,  Steven Langdon ,  Thomas Feudel

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28167 ,  H01L21/31138 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： Methods are provided for fabricating integrated circuits using non-oxidizing resist removal. In accordance with one embodiment the method includes forming a gate electrode structure overlying a semiconductor substrate and applying and patterning a layer of resist to expose a portion of the semiconductor substrate adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate using the gate electrode structure and the layer of resist as an implant mask. The layer of resist is removed in a non-oxidizing ambient and the implanted conductivity determining ions are activated by thermal annealing.

摘要翻译： 提供了使用非氧化抗蚀剂去除制造集成电路的方法。 根据一个实施例，该方法包括形成覆盖在半导体衬底上的栅电极结构，并施加和构图抗蚀剂层以暴露与栅电极结构相邻的半导体衬底的一部分。 使用栅电极结构和抗蚀剂层作为植入掩模将电导率确定离子注入到半导体衬底中。 在非氧化环境中去除抗蚀剂层，并且通过热退火来激活注入的电导率确定离子。

公开(公告)号：US20130256901A1

公开(公告)日：2013-10-03

申请号：US13436323

申请日：2012-03-30

申请人： Thilo Scheiper ,  Stefan Flachowsky ,  Jan Hoentschel

发明人： Thilo Scheiper ,  Stefan Flachowsky ,  Jan Hoentschel

IPC分类号： H01L21/768 ,  H01L23/48 ,  B82Y40/00

CPC分类号： H01L21/76816 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.

摘要翻译： 提供了具有基板触点的集成电路的制造方法和具有基板触点的集成电路。 一种方法包括在穿过掩埋绝缘层延伸到硅衬底的SOI衬底中形成第一沟槽。 在由第一沟槽暴露的硅衬底中形成金属硅化物区域。 第一应力诱导层形成在金属硅化物区域之上。 第二应力诱导层形成在第一应力诱导层上。 介电材料的ILD层形成在第二应力诱导层上。 形成延伸穿过ILD层和第一和第二应力诱导层到金属硅化物区域的第二沟槽。 第二沟槽填充有导电材料。

公开(公告)号：US20130244388A1

公开(公告)日：2013-09-19

申请号：US13421604

申请日：2012-03-15

申请人： Thilo Scheiper ,  Stefan Flachowsky ,  Shesh Mani Pandey

发明人： Thilo Scheiper ,  Stefan Flachowsky ,  Shesh Mani Pandey

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/26586 ,  H01L21/823418 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a gate stack on a semiconductor substrate. In the method, a first halo implantation is performed on the semiconductor substrate with a first dose of dopant ions to form first halo regions therein. A second halo spacer is formed around the gate stack. Then a second halo implantation is performed on the semiconductor substrate with a second dose of dopant ions to form second halo regions therein.

摘要翻译： 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成栅叠层。 在该方法中，在第一剂量的掺杂剂离子的半导体衬底上进行第一晕圈注入，以在其中形成第一晕圈。 在栅堆叠周围形成第二晕环。 然后在第二剂量的掺杂剂离子的半导体衬底上进行第二晕圈注入，以在其中形成第二晕圈。

公开(公告)号：US08524566B2

公开(公告)日：2013-09-03

申请号：US13331951

申请日：2011-12-20

申请人： Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823425

摘要： Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device.

摘要翻译： 提供了一种用于制造集成电路的方法的实施例。 在一个实施例中，该方法包括产生部分完成的半导体器件，其包括衬底，源极/漏极（S / D）区域，S / D区域之间的沟道区域和沟道区域上的栅极堆叠。 在至少一个S / D区域上形成至少一个凸起的导电结构，并且通过横向间隙与栅极堆叠分离。 然后，升高的导电结构被反蚀刻以增加横向间隙的宽度，并且在完成的半导体器件的操作期间减小凸起的导电结构和栅极堆叠之间的寄生边缘电容。