摘要:
A technique that improves both processor performance and associated data bandwidth through user-defined interfaces that can be added to a configurable and extensible microprocessor core. These interfaces can be used to communicate status or control information and to achieve synchronization between the processor and any external device including other processors. These interfaces can also be used to achieve data transfer at the rate of one data element per interface in every clock cycle. This technique makes it possible to design multiprocessor SOC systems with high-speed data transfer between processors without using the memory subsystem. Such a system and design methodology offers a complete shift from the standard bus-based architecture and allows designers to treat processors more like true computational units, so that designers can more effectively utilize programmable solutions rather than design dedicated hardware. This can have dramatic effects not only in the performance and bandwidth achieved by designs, but also in the time to market and reuse of such designs.
摘要:
A technique that improves both processor performance and associated data bandwidth through user-defined interfaces that can be added to a configurable and extensible microprocessor core. These interfaces can be used to communicate status or control information and to achieve synchronization between the processor and any external device including other processors. These interfaces can also be used to achieve data transfer at the rate of one data element per interface in every clock cycle. This technique makes it possible to design multiprocessor SOC systems with high-speed data transfer between processors without using the memory subsystem. Such a system and design methodology offers a complete shift from the standard bus-based architecture and allows designers to treat processors more like true computational units, so that designers can more effectively utilize programmable solutions rather than design dedicated hardware. This can have dramatic effects not only in the performance and bandwidth achieved by designs, but also in the time to market and reuse of such designs.
摘要:
A multiprocessor computer system comprises a plurality of processing element nodes and an interconnect network interconnecting the plurality of processing element nodes. An interface circuit is associated with each one of the plurality of processing element nodes. The interface circuit has a lookup table having n-number of routing entries for a given destination node. Each one of the n-number of routing entries associated with a different class of traffic. The network traffic is routed according to the class.
摘要:
Methods for testing a [A] tape carrier package (TCP) for an integrated circuit device that includes two sets of test pads. A first set of test pads are located along the outer edges of the TCP and are used to test the performance of the integrated circuit device once the TCP has been fabricated and assembled. A second set of test pads is also provided between the TCP outer leads and integrated circuit device for testing the performance of the device once the TCP has been removed from a printed circuit board.
摘要:
Certain cycloalkyl-type compounds have been found to be useful as isotropic dyestuffs in guest-host combinations with nematic, cholesteric and smectic liquid crystals and other well-known dichroic dyestuffs. By "isotropic" it is meant that the disclosed dyestuffs have optical order parameters (S) very close to zero. Use of the disclosed isotropic dyestuffs with additional well-known dichroic dyes in liquid crystal display devices, provides displays which alter between one colored state and another, depending upon the presence or absence of an electric field across the display.
摘要:
A composition for use in liquid crystal display devices, consisting essentially of a nematic liquid crystal material and a helichromic compound possessing both a chromophoric moiety and a helical ordering moiety. The helical ordering moiety is capable of helically ordering the mixture of liquid crystal material and helichromic compound. The helichromic compound can be utilized in conventional "guest-host" and "twist nematic" displays as well as in unique helichromic displays. When used in helichromic displays, the helichromic compounds eliminate after-image scattering and enable the display to be operated at reduced voltages.
摘要:
Liquid crystal compositions containing pleochroic dyes. The pleochroic dyes are substituted anthraquinone dyes containing at least one carbocyclic or heterocyclic group linked to the anthraquinone moiety through a sulfur atom. The dyes are used in guest-host combinations with nematic liquid crystal compositions having positive dielectric anisotropy. Electro-optic devices containing these guest-host combinations are disclosed.
摘要:
Anils of 1,4- and 1,8-diaminoanthraquinone with p-alkyl- and p-alkoxybenzaldehyde are found to be pleochroic dyes which form guest-host combinations with dielectrically positive anisotropic nematic liquid crystals. These combinations are of value in electro-optical display devices.
摘要翻译:发现1,4-和1,8-二氨基蒽醌与对 - 烷基 - 和对 - 烷氧基苯甲醛的to to which。。。。。。。。。。。。。。。。。。。。。。。 这些组合在电光显示装置中是有价值的。
摘要:
The present invention provides an interface and method for synchronous data transfer between domains clocked at different frequencies. The interface includes a first latch for receiving data from a first domain clocked at one frequency when the first latch is selected and a second latch for receiving data from the first domain when the second latch is selected. A third latch is provided for transferring data from either the first latch or the second latch to the second domain when the second domain is clocked.
摘要:
A method and system for communicating to a sender an availability of receiving a new message includes providing buffers having at least one corresponding slot for storing a message and providing a credit signal that communicates to the sender only when all of the buffers have at least one of the corresponding slot available for storing a new message. Each of the buffers is monitored for whether at least one of the corresponding slots is available for storing the new message. A corresponding receiver counter is provided for each of the buffers. Each receiver counter is decremented when all of the buffers have at least one corresponding slot available for storing the new message. Each of the buffers is configured to receive a corresponding particular message type. The particular message type of the new message is determined. The new message is loaded into the corresponding slot of one of the buffers which is configured for receiving the particular message type of the new message. The counter of each of the buffers in which the new message was not loaded is incremented. After the loaded new message is freed from the buffer in which it was loaded, the counter of the buffer in which the new message was loaded is incremented.