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    Methods for fabricating a metal-oxide-semiconductor device structure
    31.
    发明授权
    Methods for fabricating a metal-oxide-semiconductor device structure 有权
    金属氧化物半导体器件结构的制造方法

    公开(公告)号：US07951660B2

    公开(公告)日：2011-05-31

    申请号：US10703355

    申请日：2003-11-07

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Larry Alan Nesbit

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Larry Alan Nesbit

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66772 ,  H01L21/2807 ,  H01L29/4908

    摘要： A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

    摘要翻译： 一种制造金属氧化物半导体器件结构的方法。 该方法包括通过离子注入将掺杂剂物质同时引入覆盖在半导体有源层上的绝缘层和栅电极的半导体有源层中。 选择半导体有源层的厚度，栅电极的厚度和掺杂剂物质的动能，使得半导体有源层和绝缘层中的掺杂剂物质的投影范围位于绝缘层内，并且投影 栅电极中的掺杂物种类的范围位于栅电极内。 结果，半导体有源层和栅电极可以在单个离子注入期间同时掺杂，而不需要另外的注入掩模。

    Layer patterning using double exposure processes in a single photoresist layer
    32.
    发明授权
    Layer patterning using double exposure processes in a single photoresist layer 有权
    在单一光致抗蚀剂层中使用双曝光工艺的层图案化

    公开(公告)号：US07923202B2

    公开(公告)日：2011-04-12

    申请号：US11831099

    申请日：2007-07-31

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

    IPC分类号： G03F7/26

    CPC分类号： G03F7/2024 ,  G03F7/38 ,  G03F7/40 ,  G03F7/70425

    摘要： A structure and a method for forming the same. The method includes providing a structure which includes (a) a to-be-patterned layer, (b) a photoresist layer on top of the to-be-patterned layer wherein the photoresist layer includes a first opening, and (c) a cap region on side walls of the first opening. A first top surface of the to-be-patterned layer is exposed to a surrounding ambient through the first opening. The method further includes performing a first lithography process resulting in a second opening in the photoresist layer. The second opening is different from the first opening. A second top surface of the to-be-patterned layer is exposed to a surrounding ambient through the second opening.

    摘要翻译： 一种结构及其形成方法。 该方法包括提供一种结构，其包括（a）待图案化层，（b）在待图案化层的顶部上的光致抗蚀剂层，其中光致抗蚀剂层包括第一开口，和（c）帽 区域在第一开口的侧壁上。 待图案化层的第一顶表面通过第一开口暴露于周围环境。 该方法还包括执行在光致抗蚀剂层中产生第二开口的第一光刻工艺。 第二个开口与第一个开口不同。 待图案化层的第二顶表面通过第二开口暴露于周围环境。

    Sidewall image transfer processes for forming multiple line-widths
    34.
    发明授权
    Sidewall image transfer processes for forming multiple line-widths 失效
    用于形成多个线宽的侧壁图像传输过程

    公开(公告)号：US07699996B2

    公开(公告)日：2010-04-20

    申请号：US11680204

    申请日：2007-02-28

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III

    IPC分类号： H01B13/00

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123

    摘要： A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD

    摘要翻译： 同时形成多个线宽的方法，其中之一小于使用常规光刻技术可实现的线宽。 该方法包括提供在存储层顶部包括存储层和侧壁图像传输（SIT）层的结构。 然后，对SIT层进行图案化，形成SIT区域。 然后，在存储层的定向蚀刻期间，将SIT区域用作阻挡掩模，产生第一存储区域。 然后，SIT区域的侧壁在参考方向上退回退避距离D，导致SIT部分。 所述图案化包括光刻工艺。 退回距离D小于与光刻工艺相关联的关键尺寸CD。 SIT区域包括参考方向上的第一维度W2和第二维度W3，其中CD

    Memory devices using carbon nanotube (CNT) technologies
    38.
    发明授权
    Memory devices using carbon nanotube (CNT) technologies 有权
    使用碳纳米管（CNT）技术的存储器件

    公开(公告)号：US07483285B2

    公开(公告)日：2009-01-27

    申请号：US12018915

    申请日：2008-01-24

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

    IPC分类号： G11C11/00

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0512

    摘要： Structures for memory devices. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

    摘要翻译： 存储器件结构。 该结构包括（a）基底; （b）基板上的第一和第二电极区域; 和（c）设置在第一和第二电极区之间的第三电极区。 响应于施加在第一和第三电极区域之间的第一写入电压电位，第三电极区域改变其自身形状，使得响应于随后施加在第一和第三电极区域之间的预先指定的读取电压电势，感测 电流在第一和第三电极区域之间流动。 此外，响应于施加在第二和第三电极区域之间的第二写入电压电位，第三电极区域改变其自身形状，使得响应于施加在第一和第三电极区域之间的预先设定的读取电压电位， 所述感测电流不在第一和第三电极区域之间流动。

    Memory devices using carbon nanotube (CNT) technologies
    39.
    发明授权
    Memory devices using carbon nanotube (CNT) technologies 有权
    使用碳纳米管（CNT）技术的存储器件

    公开(公告)号：US07385839B2

    公开(公告)日：2008-06-10

    申请号：US11275010

    申请日：2005-12-01

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

    IPC分类号： G11C11/00

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0512

    摘要： Structures and methods for operating the same. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

    摘要翻译： 结构和操作方法。 该结构包括（a）基底; （b）基板上的第一和第二电极区域; 和（c）设置在第一和第二电极区之间的第三电极区。 响应于施加在第一和第三电极区域之间的第一写入电压电位，第三电极区域改变其自身形状，使得响应于随后施加在第一和第三电极区域之间的预先指定的读取电压电势，感测 电流在第一和第三电极区域之间流动。 此外，响应于施加在第二和第三电极区域之间的第二写入电压电位，第三电极区域改变其自身形状，使得响应于施加在第一和第三电极区域之间的预先设定的读取电压电位， 所述感测电流不在第一和第三电极区域之间流动。