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公开(公告)号：US20160336227A1
公开(公告)日：2016-11-17
申请号：US14709083
申请日：2015-05-11
Applicant: United Microelectronics Corp.
Inventor： Pin-Hong Chen , Kuo-Chih Lai , Chia-Chang Hsu , Chun-Chieh Chiu , Li-Han Chen , Shu-Min Huang , Min-Chuan Tsai , Hsin-Fu Huang , Chi-Mao Hsu
IPC: H01L21/768
CPC classification number: H01L21/76895 , H01L21/28518 , H01L21/76805 , H01L21/76816 , H01L21/76843 , H01L21/76855 , H01L21/76889 , H01L21/76897 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53266
Abstract: A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening penetrates through the composite dielectric layer and exposes a portion of the source/drain region. A titanium nitride layer is formed in the opening, and the titanium nitride layer is in contact with the exposed portion of the source/drain region. The titanium nitride layer is annealed, so that the bottom portion of the titanium nitride layer is partially transformed into a titanium silicide layer. A conductive layer is formed to fill up the opening.
Abstract translation: 提供一种形成接触结构的方法。 含硅基板上形成有复合电介质层。 开口穿过复合介电层并暴露出源/漏区的一部分。 在开口中形成氮化钛层，氮化钛层与源极/漏极区域的露出部分接触。 将氮化钛层退火，使得氮化钛层的底部部分转变为硅化钛层。 形成导电层以填充开口。
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公开(公告)号：US12075613B2
公开(公告)日：2024-08-27
申请号：US17570345
申请日：2022-01-06
Inventor： Pin-Hong Chen , Yi-Wei Chen , Tzu-Chieh Chen , Chih-Chieh Tsai , Chia-Chen Wu , Kai-Jiun Chang , Yi-An Huang , Tsun-Min Cheng
IPC: H10B12/00
CPC classification number: H10B12/488 , H10B12/34
Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.
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公开(公告)号：US11222784B2
公开(公告)日：2022-01-11
申请号：US16831827
申请日：2020-03-27
Inventor： Tzu-Hao Liu , Yi-Wei Chen , Tsun-Min Cheng , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Po-Chih Wu , Pin-Hong Chen , Chun-Chieh Chiu , Tzu-Chieh Chen , Chih-Chien Liu , Chih-Chieh Tsai , Ji-Min Lin
IPC: H01L21/28 , G11C11/4097 , H01L27/108
Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.
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34.发明申请公开(公告)号：US20200266199A1
公开(公告)日：2020-08-20
申请号：US16866573
申请日：2020-05-05
Inventor： Chih-Chieh Tsai , Pin-Hong Chen , Tzu-Chieh Chen , Tsun-Min Cheng , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Shih-Fang Tzou
IPC: H01L27/108
Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.
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公开(公告)号：US20200227264A1
公开(公告)日：2020-07-16
申请号：US16831827
申请日：2020-03-27
Inventor： Tzu-Hao Liu , Yi-Wei Chen , Tsun-Min Cheng , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Po-Chih Wu , Pin-Hong Chen , Chun-Chieh Chiu , Tzu-Chieh Chen , Chih-Chien Liu , Chih-Chieh Tsai , Ji-Min Lin
IPC: H01L21/28 , G11C11/4097 , H01L27/108
Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.
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Patent Agency Ranking
公开(公告)号：US10475799B2
公开(公告)日：2019-11-12
申请号：US15901875
申请日：2018-02-21
Inventor： Pin-Hong Chen , Yi-Wei Chen , Chih-Chieh Tsai , Tzu-Chieh Chen , Tsun-Min Cheng , Chi-Mao Hsu
IPC: H01L27/108
Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.
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公开(公告)号：US10465287B2
公开(公告)日：2019-11-05
申请号：US15919191
申请日：2018-03-12
Inventor： Chih-Chien Liu , Pin-Hong Chen , Tsun-Min Cheng , Yi-Wei Chen
IPC: C23C16/455 , H01L21/768 , H01L23/544 , H01L21/285 , H01L21/321 , C23C16/02 , C23C16/34
Abstract: A semiconductor device includes a substrate, a dielectric layer, a first tungsten layer, an interface layer and a second tungsten layer. The dielectric layer is disposed on the substrate and has a first opening and a second opening larger than the first opening. The first tungsten layer is filled in the first opening and is disposed in the second opening. The second tungsten layer is disposed on the first tungsten layer in the second opening, wherein the second tungsten layer has a grain size gradually increased from a bottom surface to a top surface. The interface layer is disposed between the first tungsten layer and the second tungsten layer, wherein the interface layer comprises a nitrogen containing layer. The present invention further includes a method of forming a semiconductor device.
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公开(公告)号：US10374051B1
公开(公告)日：2019-08-06
申请号：US15987891
申请日：2018-05-23
Inventor： Ji-Min Lin , Yi-Wei Chen , Tsun-Min Cheng , Pin-Hong Chen , Chih-Chien Liu , Chun-Chieh Chiu , Tzu-Chieh Chen , Chih-Chieh Tsai , Yi-An Huang , Kai-Jiun Chang
IPC: H01L29/49 , H01L29/423 , H01L21/28 , H01L21/8234 , H01L29/43
Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a metal silicon nitride layer on the silicon layer; forming a stress layer on the metal silicon nitride layer; performing a thermal treatment process; removing the stress layer; forming a conductive layer on the metal silicon nitride layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
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公开(公告)号：US20190237468A1
公开(公告)日：2019-08-01
申请号：US15901875
申请日：2018-02-21
Inventor： Pin-Hong Chen , Yi-Wei Chen , Chih-Chieh Tsai , Tzu-Chieh Chen , Tsun-Min Cheng , Chi-Mao Hsu
IPC: H01L27/108
Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.
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40.发明申请公开(公告)号：US20190067296A1
公开(公告)日：2019-02-28
申请号：US15712151
申请日：2017-09-22
Inventor： Pin-Hong Chen , Yi-Wei Chen , Tzu-Chieh Chen , Chih-Chieh Tsai , Chia-Chen Wu , Kai-Jiun Chang , Yi-An Huang , Tsun-Min Cheng
IPC: H01L27/108
Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.
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