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公开(公告)号：US12106962B2
公开(公告)日：2024-10-01
申请号：US17341183
申请日：2021-06-07
发明人： Yi Jing Wang , Chia-Chang Hsu , Chien-Hao Chen , Chang-Mao Wang , Chun-Chi Yu
IPC分类号： H01L21/033 , G03F7/00 , G03F7/20 , H01L21/311 , H01L21/66 , H01L23/544
CPC分类号： H01L21/0337 , G03F7/2022 , G03F7/70633 , H01L21/31144 , H01L22/20 , H01L23/544
摘要： The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.
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公开(公告)号：US20230301201A1
公开(公告)日：2023-09-21
申请号：US18201741
申请日：2023-05-24
发明人： Chih-Wei Kuo , Chia-Chang Hsu
CPC分类号： H10N50/80 , H01L27/0248 , H10B61/22
摘要： A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.
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公开(公告)号：US11706995B2
公开(公告)日：2023-07-18
申请号：US17165837
申请日：2021-02-02
发明人： Chih-Wei Kuo , Chia-Chang Hsu
CPC分类号： H10N50/80 , H01L27/0248 , H10B61/22
摘要： A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.
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公开(公告)号：US20220216395A1
公开(公告)日：2022-07-07
申请号：US17165837
申请日：2021-02-02
发明人： Chih-Wei Kuo , Chia-Chang Hsu
摘要： A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.
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公开(公告)号：US10937946B2
公开(公告)日：2021-03-02
申请号：US16541172
申请日：2019-08-15
发明人： Hui-Lin Wang , Chia-Chang Hsu , Rai-Min Huang
摘要： A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.
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公开(公告)号：US10340350B2
公开(公告)日：2019-07-02
申请号：US16044581
申请日：2018-07-25
发明人： Shih-Min Chou , Yun-Tzu Chang , Wei-Ning Chen , Wei-Ming Hsiao , Chia-Chang Hsu , Kuo-Chih Lai , Yang-Ju Lu , Yen-Chen Chen , Chun-Yao Yang
IPC分类号： H01L29/76 , H01L29/94 , H01L29/423 , H01L29/06 , H01L29/49 , H01L29/51 , H01L21/02 , H01L21/28 , H01L21/762 , H01L27/088 , H01L27/092 , H01L21/8238 , H01L21/3213 , H01L21/8234
摘要： A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
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公开(公告)号：US09570348B2
公开(公告)日：2017-02-14
申请号：US14709083
申请日：2015-05-11
发明人： Pin-Hong Chen , Kuo-Chih Lai , Chia-Chang Hsu , Chun-Chieh Chiu , Li-Han Chen , Shu-Min Huang , Min-Chuan Tsai , Hsin-Fu Huang , Chi-Mao Hsu
IPC分类号： H01L21/768
CPC分类号： H01L21/76895 , H01L21/28518 , H01L21/76805 , H01L21/76816 , H01L21/76843 , H01L21/76855 , H01L21/76889 , H01L21/76897 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53266
摘要： A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening penetrates through the composite dielectric layer and exposes a portion of the source/drain region. A titanium nitride layer is formed in the opening, and the titanium nitride layer is in contact with the exposed portion of the source/drain region. The titanium nitride layer is annealed, so that the bottom portion of the titanium nitride layer is partially transformed into a titanium silicide layer. A conductive layer is formed to fill up the opening.
摘要翻译： 提供一种形成接触结构的方法。 含硅基板上形成有复合电介质层。 开口穿过复合介电层并暴露出源/漏区的一部分。 在开口中形成氮化钛层，氮化钛层与源极/漏极区域的露出部分接触。 将氮化钛层退火，使得氮化钛层的底部部分转变为硅化钛层。 形成导电层以填充开口。
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8.发明授权公开(公告)号：US09482964B2
公开(公告)日：2016-11-01
申请号：US14279039
申请日：2014-05-15
发明人： En-Chiuan Liou , Chia-Chang Hsu , Yi-Ting Chen , Teng-Chin Kuo , Chun-Chi Yu
IPC分类号： G03F7/20
CPC分类号： G03F7/70516
摘要： An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.
摘要翻译： 提供重叠标记集以具有两个位于相同图案层的至少第一和第二重叠标记。 第一重叠标记包括至少两组X方向线性图案，其间具有预置偏移量a1; 以及至少两组Y方向线性图案，其间具有预设偏移量a1。 第二重叠标记包括至少两组X方向线性图案，其间具有预设偏移量b1; 以及至少两组Y方向线性图案，其间具有预设的偏移量b1。 预置偏移量a1和b1不相等。
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公开(公告)号：US12029138B2
公开(公告)日：2024-07-02
申请号：US18201741
申请日：2023-05-24
发明人： Chih-Wei Kuo , Chia-Chang Hsu
CPC分类号： H10N50/80 , H01L27/0248 , H10B61/22
摘要： A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.
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公开(公告)号：US20240032440A1
公开(公告)日：2024-01-25
申请号：US18376437
申请日：2023-10-03
发明人： Hui-Lin Wang , Chia-Chang Hsu , Chen-Yi Weng , Chin-Yang Hsieh , Jing-Yin Jhang
CPC分类号： H10N50/80 , H01F41/34 , H01F10/3254 , G11C11/161 , H10B61/00 , H10N50/01 , H10N50/85
摘要： A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.
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