公开(公告)号：US09870256B2

公开(公告)日：2018-01-16

申请号：US13572921

申请日：2012-08-13

申请人： Rui Hou ,  Yi Ge ,  Kun Wang ,  Zhen Bo Zhu

发明人： Rui Hou ,  Yi Ge ,  Kun Wang ,  Zhen Bo Zhu

IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F9/48 ,  G06F9/54

CPC分类号： G06F9/4843 ,  G06F9/54 ,  G06F2209/509

摘要： Provided is a hardware accelerator and method, central processing unit, and computing device. A hardware accelerating method includes, in response to a request for a new task issued by a hardware thread, accelerating processing of the new task and producing a processing result for the task. A predicting step predicts total waiting time of the new task for returning to a specified address associated with the hardware thread.

公开(公告)号：US08503793B2

公开(公告)日：2013-08-06

申请号：US12616894

申请日：2009-11-12

申请人： Yi Ge

发明人： Yi Ge

IPC分类号： G06K9/48

CPC分类号： G06K9/6203 ,  G06K9/00986

摘要： A correlation processing apparatus that obtains a correlation value between an image and a subimage, the apparatus including: N arithmetic circuits, each of the N arithmetic circuits performing an arithmetic operation on a first image pixel value of a first image pixel of the image and a second image pixel value of a second image pixel of the subimage; a rectangular pattern selection circuit selecting a rectangular pattern among a plurality of predetermined rectangular patterns, the rectangular pattern including Q elements, the smallest number of divisions is obtained if the image is divided by the rectangular pattern; a control circuit activating Q arithmetic circuits among the N arithmetic circuits and identifying Q first image pixel values and Q second image pixel values on which the arithmetic operations are performed by the Q arithmetic circuits; and an accumulator accumulating the results of the arithmetic operations performed by the Q arithmetic circuits.

摘要翻译： 一种相关处理装置，其获得图像和子图像之间的相关值，所述装置包括：N个运算电路，对所述图像的第一图像像素的第一图像像素执行算术运算的N个运算电路，以及 子图像的第二图像像素的第二图像像素值; 在多个预定矩形图案中选择矩形图案的矩形图形选择电路，包括Q个元素的矩形图案，如果图像被矩形图案分割，则获得最小分割数; 在N个算术电路中激活Q运算电路并识别由Q运算电路进行算术运算的Q个第一图像像素值和Q个第二图像像素值的控制电路; 以及累加器，其累加由Q个运算电路执行的算术运算结果。

公开(公告)号：US20130031553A1

公开(公告)日：2013-01-31

申请号：US13557211

申请日：2012-07-25

申请人： Rui Hou ,  Yi Ge ,  Kun Wang ,  Zhen Bo Zhu

发明人： Rui Hou ,  Yi Ge ,  Kun Wang ,  Zhen Bo Zhu

IPC分类号： G06F9/46

CPC分类号： G06F9/4843 ,  G06F9/54 ,  G06F2209/509

摘要： Provided is a hardware accelerator, central processing unit, and computing device. A hardware accelerator includes a task accelerating unit configured to, in response to a request for a new task issued by a hardware thread, accelerate the processing of the new task and produce a processing result for the task; a task time prediction unit configured to predict the total waiting time of the new task for returning to a specified address associated with the hardware thread. One aspect of this disclosure makes the hardware thread aware of the time to be waited for before getting a processing result, facilitating its task planning accordingly.

摘要翻译： 提供了硬件加速器，中央处理单元和计算设备。 硬件加速器包括：任务加速单元，被配置为响应于由硬件线程发出的新任务的请求，加速新任务的处理并产生该任务的处理结果; 任务时间预测单元，被配置为预测新任务的总等待时间，以返回到与硬件线程相关联的指定地址。 本公开的一个方面使得硬件线程在获得处理结果之前了解等待的时间，从而有助于其相应的任务规划。

公开(公告)号：US20100217945A1

公开(公告)日：2010-08-26

申请号：US12708634

申请日：2010-02-19

申请人： Yi Ge ,  Rui Hou ,  Huayong Wang

发明人： Yi Ge ,  Rui Hou ,  Huayong Wang

IPC分类号： G06F12/00 ,  G06F12/06

CPC分类号： G06F9/30105 ,  G06F9/30116 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/528

摘要： The present invention provides a method, apparatus and article of manufacture, for fast context saving in transactional memory. The method creates a mapping table that includes entries corresponding to architectural registers. Each entry includes a physical register index and shadow bit of a first physical register mapped to an architectural register. In response to a detection that an update occurs to an architectural register in a transaction and its shadow bit being an invalid value, the method sets the shadow bit to be a valid value and sets a shadow register for the architectural register using the physical register index of the first physical register. The method maps a second physical register to the shadow register in order to save a modified value generated by an update process and saves the original value before the update process by use of the first physical register corresponding to the architecture register.

摘要翻译： 本发明提供了一种用于在事务存储器中快速上下文保存的方法，装置和制品。 该方法创建一个包含对应于架构寄存器的条目的映射表。 每个条目包括映射到架构寄存器的第一物理寄存器的物理寄存器索引和影像位。 响应于检测到交易中的体系结构寄存器发生更新，并且其影子位是无效值，则该方法将阴影位设置为有效值，并使用物理寄存器索引为体系结构寄存器设置影子寄存器 的第一个物理登记册。 该方法将第二个物理寄存器映射到影子寄存器，以便保存由更新过程生成的修改值，并通过使用对应于架构寄存器的第一个物理寄存器在更新过程之前保存原始值。

公开(公告)号：US20080243748A1

公开(公告)日：2008-10-02

申请号：US11343991

申请日：2006-01-31

申请人： Zhi Yong Liang ,  Yong Hua Lin ,  Kai Zheng ,  Yi Ge ,  Yan Qi Wang

发明人： Zhi Yong Liang ,  Yong Hua Lin ,  Kai Zheng ,  Yi Ge ,  Yan Qi Wang

IPC分类号： G06N5/02

CPC分类号： H04L45/48 ,  H04L45/745 ,  H04L47/2441 ,  H04L69/22

摘要： The present invention provides a rule set partitioning based packet classification method for Internet. The method comprising: performing Horizontal Cut for the rule set, determining the field for partitioning a rule layer based on a target algorithm and selecting the partition manner of the Horizontal Cut, performing Horizontal Cut according to the selected partition manner of the Horizontal Cut, thereby obtaining more than one rule layers, each rule layer being a Horizontal subset, combining the rule layers to obtain a plurality of Horizontal subsets according to the total number of the pre-designated Horizontal subsets and a predefined principle, wherein the total number of said combined plurality of Horizontal subsets equals to the total number of said pre-designated Horizontal subsets; performing Vertical Cut in each of the Horizontal subsets; then forming a Hash table that can index the Vertical subsets, so that it can be used in a lookup; and realizing rule storage in each Vertical subset respectively according to the target algorithm.

摘要翻译： 本发明提供了一种用于因特网的基于规则集划分的分组分类方法。 该方法包括：对规则集执行水平切割，基于目标算法确定用于划分规则层的字段，并选择水平切割的分割方式，根据所选择的水平切割分割方式进行水平切割，由此 获取多于一个的规则层，每个规则层是一个水平子集，根据预先指定的水平子集的总数和一个预定原则组合规则层以获得多个水平子集，其中所述组合的总数 多个水平子集等于所述预先指定的水平子集的总数; 在每个水平子集中执行垂直切割; 然后形成可以对“垂直”子集进行索引的哈希表，以便可以在查找中使用; 并根据目标算法分别在每个垂直子集中实现规则存储。

公开(公告)号：US20060123253A1

公开(公告)日：2006-06-08

申请号：US11007098

申请日：2004-12-07

申请人： Bryan Morgan ,  Premanand Sakarda ,  Priya Vaidya ,  Yi Ge ,  Zhou Gao ,  Swee-chin Pang ,  Manoj Thadani ,  Canhui Yuan

发明人： Bryan Morgan ,  Premanand Sakarda ,  Priya Vaidya ,  Yi Ge ,  Zhou Gao ,  Swee-chin Pang ,  Manoj Thadani ,  Canhui Yuan

IPC分类号： G06F1/26

CPC分类号： G06F1/3228 ,  G06F1/324 ,  Y02D10/126

摘要： A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.

摘要翻译： 处理系统可以包括性能监视单元（PMU），机器可访问介质和响应于PMU和机器可访问介质的处理器。 在机器可访问介质中编码的指令在由处理器执行时可以至少部分地基于用于处理系统的预定监视策略来确定是否应该收集处理系统的性能细节。 该指令可以至少部分地基于从PMU获得的数据来生成处理系统的性能数据。 所述指令可以至少部分地基于所述处理系统的性能数据和功率策略简档来确定所述处理系统是否应被重新配置。 该指令可以通过使用PMU重新配置处理系统来自动调整处理系统的功耗。 描述和要求保护其他实施例。

公开(公告)号：US08392660B2

公开(公告)日：2013-03-05

申请号：US12453782

申请日：2009-05-21

申请人： Yi Ge ,  Shinichiro Tago

发明人： Yi Ge ,  Shinichiro Tago

IPC分类号： G06F12/00

CPC分类号： G06F12/123 ,  G06F12/0811 ,  G06F12/128 ,  G06F2212/271

摘要： A cache system includes processing units operative to access a main memory device, caches coupled in one-to-one correspondence to the processing units, and a controller coupled to the caches to control data transfer between the caches and data transfer between the main memory and the caches, wherein the controller includes a memory configured to store first information and second information separately for each index, the first information indicating an order of oldness of entries in each one of the caches, and the second information indicating an order of oldness of entries for the plurality of the caches, and a logic circuit configured to select an entry to be evicted and its destination in response to the first and second information when an entry of an index corresponding to an accessed address is to be evicted from a cache corresponding to the processing unit that accesses the main memory device.

公开(公告)号：US20130031554A1

公开(公告)日：2013-01-31

申请号：US13572921

申请日：2012-08-13

申请人： Rui Hou ,  Yi Ge ,  Kun Wang ,  Zhen Bo Zhu

发明人： Rui Hou ,  Yi Ge ,  Kun Wang ,  Zhen Bo Zhu

IPC分类号： G06F9/46

CPC分类号： G06F9/4843 ,  G06F9/54 ,  G06F2209/509

摘要： Provided is a hardware accelerator and method, central processing unit, and computing device. A hardware accelerating method includes, in response to a request for a new task issued by a hardware thread, accelerating processing of the new task and producing a processing result for the task. A predicting step predicts total waiting time of the new task for returning to a specified address associated with the hardware thread.

摘要翻译： 提供了一种硬件加速器和方法，中央处理单元和计算设备。 硬件加速方法包括响应于由硬件线程发出的新任务的请求，加速新任务的处理并产生任务的处理结果。 预测步骤预测新任务返回到与硬件线程相关联的指定地址的总等待时间。

公开(公告)号：US20120288088A1

公开(公告)日：2012-11-15

申请号：US13469396

申请日：2012-05-11

申请人： Xiao Tao Chang ,  Yi Ge ,  Chun Liang Gu ,  Kun Wang ,  Qiong Zou

发明人： Xiao Tao Chang ,  Yi Ge ,  Chun Liang Gu ,  Kun Wang ,  Qiong Zou

IPC分类号： G06F21/24

CPC分类号： H04L69/04 ,  H04L9/0618 ,  H04L63/0272 ,  H04L2209/30

摘要： A method and system for compressing and encrypting data. The method includes: receiving original data; performing a first compression of the original data to obtain a first compression result; and encrypting only a literal portion in the first compression result to obtain an encrypted first compression result. Various embodiments improve the efficiency of the process of compression and encryption to a great extent by encrypting only the literal portion of the compression result.

摘要翻译： 一种用于压缩和加密数据的方法和系统。 该方法包括：接收原始数据; 执行原始数据的第一压缩以获得第一压缩结果; 并且仅在第一压缩结果中加密文字部分以获得加密的第一压缩结果。 各种实施例通过仅加密压缩结果的文字部分在很大程度上提高了压缩和加密过程的效率。

公开(公告)号：US08286001B2

公开(公告)日：2012-10-09

申请号：US12173112

申请日：2008-07-15

申请人： Hang J. Ye ,  Tao Zhou ,  Weikai Xie ,  Guo H. Lin ,  Yi Ge

发明人： Hang J. Ye ,  Tao Zhou ,  Weikai Xie ,  Guo H. Lin ,  Yi Ge

IPC分类号： H04L29/06

CPC分类号： G06F12/1408 ,  G06F12/1009 ,  G06F21/10 ,  G06F21/125 ,  G06F21/72 ,  H04L9/0894

摘要： The present invention provides a central processing unit for processing at least one encrypted software. The encrypted software comprises at least one encrypted software section. The encrypted software section is encrypted with a management key MK, and the MK being encrypted with a device key DK as a encrypted MK. The central processing unit comprises processing and cache unit, and cryptographic unit. The cryptographic unit comprises device key storage unit for storing the DK, a plurality of management key storage units for storing MKs, wherein each management key storage unit corresponding to a management key index MKI, and decryption unit. The decryption unit decrypts a encrypted MK with the DK to obtain a MK, stores the MK to a management key storage unit, and output a MKI corresponding to the management key storage unit, thus the MKI is used to correspond to the encrypted software section. Wherein, the decryption unit invokes corresponding MK according to the MKI and decrypts the encrypted software section, and directly transfers the decrypted software code and/or data to the processing and cache unit.

摘要翻译： 本发明提供一种用于处理至少一个加密软件的中央处理单元。 加密软件包括至少一个加密的软件部分。 加密的软件部分用管理密钥MK进行加密，并且使用设备密钥DK将MK加密为加密的MK。 中央处理单元包括处理和高速缓存单元和加密单元。 加密单元包括用于存储DK的设备密钥存储单元，用于存储MK的多个管理密钥存储单元，其中与管理密钥索引MKI对应的每个管理密钥存储单元和解密单元。 解密单元用DK解密加密的MK以获得MK，将MK存储到管理密钥存储单元，并输出与管理密钥存储单元相对应的MKI，因此MKI被用于对应于加密的软件部分。 其中，解密单元根据MKI调用相应的MK，解密加密的软件部分，并将解密的软件代码和/或数据直接传送到处理和高速缓存单元。