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公开(公告)号：US07215188B2
公开(公告)日：2007-05-08
申请号：US11065796
申请日：2005-02-25
IPC分类号： G05F3/02
CPC分类号： H03K19/0016 , H03K3/0375
摘要： An integrated circuit (70) includes a first power supply bus (72) and a second power supply bus (74). The first power supply bus (72) provides a first power supply voltage (VDD) to a first plurality of circuit elements (12 and 76). The second power supply bus (74) provides a second power supply voltage (LVDD) to a second plurality of circuit elements (14), where the second power supply voltage is lower than the first power supply voltage. During a normal operating mode of the integrated circuit (70), the first power supply bus (72) provides the first power supply voltage to the first plurality of circuit elements (12 and 76) and the second power supply voltage is not provided to the second plurality of circuit elements (14). During a low power operating mode, the second power supply bus (74) provides the second power supply voltage to the second plurality of circuit elements (14) and the first power supply voltage is not provided to the first plurality of circuit elements (12 and 76).
摘要翻译： 集成电路（70）包括第一电源总线（72）和第二电源总线（74）。 第一电源总线（72）向第一多个电路元件（12和76）提供第一电源电压（VDD）。 第二电源总线（74）向第二多个电路元件（14）提供第二电源电压（LVDD），其中第二电源电压低于第一电源电压。 在集成电路（70）的正常操作模式期间，第一电源总线（72）向第一多个电路元件（12和76）提供第一电源电压，并且第二电源电压不提供给 第二多个电路元件（14）。 在低功率操作模式期间，第二电源总线（74）向第二多个电路元件（14）提供第二电源电压，并且第一电源电压不提供给第一多个电路元件（12和 76）。
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公开(公告)号：US20080082873A1
公开(公告)日：2008-04-03
申请号：US11468458
申请日：2006-08-30
IPC分类号： G11C29/00
CPC分类号： G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/5004
摘要： A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.
摘要翻译： 一种方法包括具有存储器的集成电路。 存储器工作在工作电压。 确定存储器的最小工作电压的值。 最小工作电压的值存储在可能是非易失性寄存器的非易失性存储器位置。 然后可以使用该最小工作电压信息来确定什么时候可以将替代电源电压切换到存储器或确保以其他方式满足最小电压。 最小电压只能用于集成电路内部，也可以在用户外部使用。
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33.发明授权In a data processor a method and apparatus for performing a floating-point comparison operation 失效在数据处理器中，执行浮点比较操作的方法和装置
公开(公告)号：US5357237A
公开(公告)日：1994-10-18
申请号：US941011
申请日：1992-09-04
摘要： A data processor (10) has a floating-point execution unit (32) for executing a floating-point compare operation using two data operands. The execution unit (32) uses mantissa comparator logic (107) to perform a bit-wise comparison of a mantissa portion of a first operand with the mantissa portion of a second operand, and to provide a mantissa comparison result. Similarly, exponent comparator logic (122) performs a bit-wise comparison of an exponent portion of the first operand with the exponent portion of the second, and provides an exponent comparison result. Comparator logic (114) in the execution unit receives the mantissa comparison result and the exponent comparison result. If the exponent portions of the two operands are not equal, the comparator logic (114) uses an operand sign bit of each operand and the exponent comparison result to order the two operands. If the exponent portions of the two operands are equal, the comparator logic uses the operand sign bit of each operand and the mantissa comparison result to order the two operands.
摘要翻译： 数据处理器（10）具有用于使用两个数据操作数执行浮点比较操作的浮点执行单元（32）。 执行单元（32）使用尾数比较器逻辑（107）来执行第一操作数的尾数部分与第二操作数的尾数部分的逐位比较，并提供尾数比较结果。 类似地，指数比较器逻辑（122）执行第一操作数的指数部分与第二操作数的指数部分的逐位比较，并提供指数比较结果。 执行单元中的比较器逻辑（114）接收尾数比较结果和指数比较结果。 如果两个操作数的指数部分不相等，则比较器逻辑（114）使用每个操作数的操作数符号位和指数比较结果对两个操作数进行排序。 如果两个操作数的指数部分相等，则比较器逻辑使用每个操作数的操作数符号位和尾数比较结果来排序两个操作数。
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34.发明授权公开(公告)号：US07292495B1
公开(公告)日：2007-11-06
申请号：US11427610
申请日：2006-06-29
申请人： Prashant U. Kenkare , Andrew C. Russell , David R. Bearden , James D. Burnett , Troy L. Cooper , Shayan Zhang
发明人： Prashant U. Kenkare , Andrew C. Russell , David R. Bearden , James D. Burnett , Troy L. Cooper , Shayan Zhang
IPC分类号： G11C7/00
CPC分类号： G11C11/417 , G11C5/147 , G11C11/419
摘要： An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells. The integrated circuit may further include a second power supply voltage terminal for receiving a second power supply voltage higher than the first power supply voltage, wherein the second power supply voltage is provided to power the plurality of memory cells during a second access operation of the plurality of memory cells.
摘要翻译： 提供具有低电压读/写操作的集成电路。 集成电路可以包括处理器和以行和列组织并且耦合到处理器的多个存储单元，其中存储单元行包括字线和耦合到字线的所有存储器单元，并且其中列 的存储器单元包括位线和耦合到位线的所有存储器单元。 集成电路还可以包括用于接收第一电源电压的第一电源电压端子，其中提供第一电源电压以为处理器供电，并且其中提供第一电源电压以在多个存储器单元期间供电 多个存储单元的第一访问操作。 集成电路还可以包括用于接收高于第一电源电压的第二电源电压的第二电源电压端子，其中提供第二电源电压以在多个存储器单元的第二访问操作期间为多个存储器单元供电 的记忆细胞。
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35.发明授权Iterative, noise-sensitive method of routing semiconductor nets using a delay noise threshold 有权使用延迟噪声阈值对半导体网络进行迭代，噪声敏感的方法公开(公告)号：US06480998B1
公开(公告)日：2002-11-12
申请号：US09551322
申请日：2000-04-18
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/5077
摘要： The invention relates to a new method of guidance for routing of nets in an integrated circuit model wherein all nets are first approximately routed, as with Steiner routing, and victim nets with functional delay noise above predetermined thresholds are identified. Each victim net is then detail routed. For each victim net detail routed, a set of least noise aggressive neighboring nets is selected. Segments of those neighboring nets are assigned tracks adjacent to the victim net in such a way as to maximize utilization of the victim net's neighboring tracks, thereby reducing noise induced on the victim net and maximizing use of available space on the semiconductor. The process is then repeated until there are no additional victim nets, at which point the remaining nets are detail routed.
摘要翻译： 本发明涉及一种用于在集成电路模型中网络路由的新方法，其中所有网络首先被大致路由，如同Steiner路由，并且识别出具有高于预定阈值的功能延迟噪声的受害网络。 然后，每个受害者网络将被详细路由。 对于每个受害者网络细节路由，选择一组最小噪声侵略性相邻网络。 这些相邻网络的段被分配到与受害网邻近的轨道，以便最大限度地利用受害者网络的相邻轨道，从而减少对受害者网络引起的噪声并最大限度地利用半导体上的可用空间。 然后重复该过程，直到没有额外的受害网络，此时剩余的网络被详细路由。
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36.发明授权公开(公告)号：US07542369B2
公开(公告)日：2009-06-02
申请号：US11863961
申请日：2007-09-28
申请人： Prashant U. Kenkare , Andrew C. Russell , David R. Bearden , James D. Burnett , Troy L. Cooper , Shayan Zhang
发明人： Prashant U. Kenkare , Andrew C. Russell , David R. Bearden , James D. Burnett , Troy L. Cooper , Shayan Zhang
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C5/147 , G11C11/419
摘要： An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells. The integrated circuit may further include a second power supply voltage terminal for receiving a second power supply voltage higher than the first power supply voltage, wherein the second power supply voltage is provided to power the plurality of memory cells during a second access operation of the plurality of memory cells.
摘要翻译： 提供具有低电压读/写操作的集成电路。 集成电路可以包括处理器和以行和列组织并且耦合到处理器的多个存储单元，其中存储单元行包括字线和耦合到字线的所有存储器单元，并且其中列 的存储器单元包括位线和耦合到位线的所有存储器单元。 集成电路还可以包括用于接收第一电源电压的第一电源电压端子，其中提供第一电源电压以为处理器供电，并且其中提供第一电源电压以在多个存储器单元期间供电 多个存储单元的第一访问操作。 集成电路还可以包括用于接收高于第一电源电压的第二电源电压的第二电源电压端子，其中提供第二电源电压以在多个存储器单元的第二访问操作期间为多个存储器单元供电 的记忆细胞。
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公开(公告)号：US07523373B2
公开(公告)日：2009-04-21
申请号：US11468458
申请日：2006-08-30
IPC分类号： G01R31/30
CPC分类号： G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/5004
摘要： A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.
摘要翻译： 一种方法包括具有存储器的集成电路。 存储器工作在工作电压。 确定存储器的最小工作电压值。 最小工作电压的值存储在可能是非易失性寄存器的非易失性存储器位置。 然后可以使用该最小工作电压信息来确定什么时候可以将替代电源电压切换到存储器或确保以其他方式满足最小电压。 最小电压只能用于集成电路内部，也可以在用户外部使用。
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公开(公告)号：US5565386A
公开(公告)日：1996-10-15
申请号：US478160
申请日：1995-06-07
申请人： David R. Bearden , Mark D. Bolliger
发明人： David R. Bearden , Mark D. Bolliger
IPC分类号： H01L21/28 , H01L21/82 , H01L27/118 , H03K19/00 , H01L21/60
CPC分类号： H01L27/11898
摘要： A method and structure are provided for connecting to integrated circuitry. A connectivity cell includes multiple terminals formed within the integrated circuitry. The connectivity cell further includes at least one metal layer connected to at least one of the terminals. A first area is a substantially minimal area including the connectivity cell. A second area is a substantially minimal area including at least a part of each of multiple portions of the integrated circuitry. The portions are connectable to respective ones of the terminals while having a placement flexibility relative to the terminals. This placement flexibility of the portions is substantially equal to a placement flexibility of the second area within the first area.
摘要翻译： 提供了一种用于连接到集成电路的方法和结构。 连接单元包括在集成电路内形成的多个端子。 连接单元还包括连接到至少一个端子的至少一个金属层。 第一区域是包括连接单元的基本上最小的区域。 第二区域是包括集成电路的多个部分的至少一部分的基本上最小的区域。 这些部分可连接到相应的端子，同时具有相对于端子的放置灵活性。 这些部分的放置灵活性基本上等于第一区域内的第二区域的放置灵活性。
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39.发明授权Data processor a method and apparatus for performing postnormalization in a floating-point execution unit 失效数据处理器，用于在浮点执行单元中执行后归一化的方法和装置
公开(公告)号：US5373461A
公开(公告)日：1994-12-13
申请号：US339
申请日：1993-01-04
CPC分类号： G06F7/485 , G06F2207/3856 , G06F7/49936 , G06F7/49947
摘要： A method and apparatus for performing prenormalization during execution by an execution unit (100) of a floating-point add/subtract operation using two data operands. The execution unit (100) adds a mantissa portion of a first and a second floating-point data operand to generate a prenormalized mantissa sum. The execution unit (100) minimizes critical path delays to allow high-performance floating-point calculations while simultaneously reducing logic. Instead of treating the prenormalized mantissa sum as a 64-bit value with special treatment in case of a carry out due to overflow, the floating-point adder 100 treats the prenormalized mantissa sum as a 65-bit value, with the most significant bit being a carry output. Instead of conditionally incrementing an initial exponent value, the initial exponent value is always incremented. Thus, allowing the floating-point adder unit 100 to perform the exponent adjustments for normalization and for rounding faster.
摘要翻译： 一种用于在使用两个数据操作数的浮点加法运算执行单元执行执行前正规化的方法和装置。 执行单元（100）添加第一和第二浮点数据操作数的尾数部分以生成预正规化的尾数和。 执行单元（100）使关键路径延迟最小化以允许高性能浮点计算，同时减少逻辑。 浮点加法器100将预正规化尾数和作为64位值处理，因为在进行溢出的情况下进行特殊处理，所以浮点加法器100将预正态化尾数和视为65位值，而最高有效位为 一个进位输出。 不是有条件地增加初始指数值，而是始终递增初始指数值。 因此，允许浮点加法器单元100执行用于归一化的指数调整和更快的舍入。
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