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1.发明授权In a data processor a method and apparatus for performing a floating-point comparison operation 失效在数据处理器中，执行浮点比较操作的方法和装置
公开(公告)号：US5357237A
公开(公告)日：1994-10-18
申请号：US941011
申请日：1992-09-04
摘要： A data processor (10) has a floating-point execution unit (32) for executing a floating-point compare operation using two data operands. The execution unit (32) uses mantissa comparator logic (107) to perform a bit-wise comparison of a mantissa portion of a first operand with the mantissa portion of a second operand, and to provide a mantissa comparison result. Similarly, exponent comparator logic (122) performs a bit-wise comparison of an exponent portion of the first operand with the exponent portion of the second, and provides an exponent comparison result. Comparator logic (114) in the execution unit receives the mantissa comparison result and the exponent comparison result. If the exponent portions of the two operands are not equal, the comparator logic (114) uses an operand sign bit of each operand and the exponent comparison result to order the two operands. If the exponent portions of the two operands are equal, the comparator logic uses the operand sign bit of each operand and the mantissa comparison result to order the two operands.
摘要翻译： 数据处理器（10）具有用于使用两个数据操作数执行浮点比较操作的浮点执行单元（32）。 执行单元（32）使用尾数比较器逻辑（107）来执行第一操作数的尾数部分与第二操作数的尾数部分的逐位比较，并提供尾数比较结果。 类似地，指数比较器逻辑（122）执行第一操作数的指数部分与第二操作数的指数部分的逐位比较，并提供指数比较结果。 执行单元中的比较器逻辑（114）接收尾数比较结果和指数比较结果。 如果两个操作数的指数部分不相等，则比较器逻辑（114）使用每个操作数的操作数符号位和指数比较结果对两个操作数进行排序。 如果两个操作数的指数部分相等，则比较器逻辑使用每个操作数的操作数符号位和尾数比较结果来排序两个操作数。
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2.发明授权Data processor a method and apparatus for performing postnormalization in a floating-point execution unit 失效数据处理器，用于在浮点执行单元中执行后归一化的方法和装置
公开(公告)号：US5373461A
公开(公告)日：1994-12-13
申请号：US339
申请日：1993-01-04
CPC分类号： G06F7/485 , G06F2207/3856 , G06F7/49936 , G06F7/49947
摘要： A method and apparatus for performing prenormalization during execution by an execution unit (100) of a floating-point add/subtract operation using two data operands. The execution unit (100) adds a mantissa portion of a first and a second floating-point data operand to generate a prenormalized mantissa sum. The execution unit (100) minimizes critical path delays to allow high-performance floating-point calculations while simultaneously reducing logic. Instead of treating the prenormalized mantissa sum as a 64-bit value with special treatment in case of a carry out due to overflow, the floating-point adder 100 treats the prenormalized mantissa sum as a 65-bit value, with the most significant bit being a carry output. Instead of conditionally incrementing an initial exponent value, the initial exponent value is always incremented. Thus, allowing the floating-point adder unit 100 to perform the exponent adjustments for normalization and for rounding faster.
摘要翻译： 一种用于在使用两个数据操作数的浮点加法运算执行单元执行执行前正规化的方法和装置。 执行单元（100）添加第一和第二浮点数据操作数的尾数部分以生成预正规化的尾数和。 执行单元（100）使关键路径延迟最小化以允许高性能浮点计算，同时减少逻辑。 浮点加法器100将预正规化尾数和作为64位值处理，因为在进行溢出的情况下进行特殊处理，所以浮点加法器100将预正态化尾数和视为65位值，而最高有效位为 一个进位输出。 不是有条件地增加初始指数值，而是始终递增初始指数值。 因此，允许浮点加法器单元100执行用于归一化的指数调整和更快的舍入。
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公开(公告)号：US09367475B2
公开(公告)日：2016-06-14
申请号：US13440728
申请日：2012-04-05
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.
摘要翻译： 缓存的行通常维持在低功率状态。 响应于存储器访问操作，数据处理器预测可能由操作定向的多个高速缓存行，并且将多个高速缓存行中的每一个转换为活动状态以准备它们进行访问。 基于对基本地址的一部分和偏移的对应部分的推测性解码来预测多个高速缓存行，而不执行部分的完全添加。 由于没有执行完全相加，所以可以以足够的速度执行推测解码，以便在存储器地址的完全解码完成之前允许该组行转换到活动状态。 因此，当解码完成时，与存储器地址相关联的高速缓存行可以进行访问，从而保持高速缓存访问的低延迟。
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公开(公告)号：US20120200336A1
公开(公告)日：2012-08-09
申请号：US13020565
申请日：2011-02-03
CPC分类号： H03K19/0008 , H03K19/0016
摘要： An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.
摘要翻译： 电子电路包括多个电路块，多个偏置电路，开关电路和多个晶体管。 多个电路块各自包括高功率端子和低功率端子。 开关电路包括多个开关，用于将多个偏置电路的偏置电路选择性地耦合到多个电路块的电路块的低功率端子。 多个偏置电路的每个偏置电路可以选择性地耦合到多个电路块中的每一个的低功率端子。 多个晶体管的每个晶体管具有耦合到电路接地端子的第一电流端子，并且多个晶体管中的每个晶体管具有控制端子，用于通过多个偏置的偏置电路来控制多个晶体管的导电性 电路。
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公开(公告)号：US08189408B2
公开(公告)日：2012-05-29
申请号：US12620314
申请日：2009-11-17
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1075 , G11C7/18 , G11C19/00 , G11C19/28
摘要： An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.
摘要翻译： 存储器位单元阵列可操作以提供具有数据移位能力的存储器件，从而能够以并行和串行方式从存储器件灵活地存储和检索数据。 因此，存储器阵列可以用于常规存储器存储操作，并且还可以用于提供对存储的数据元素的布置的改变的诸如矩阵操作的操作。
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公开(公告)号：US20120036398A1
公开(公告)日：2012-02-09
申请号：US13272725
申请日：2011-10-13
CPC分类号： G06F9/505 , G06F16/217 , G06F2209/504 , G06F2209/508 , Y02D10/22
摘要： A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. The processor uses the accumulated usage information in selecting processor cores to perform processor operations.
摘要翻译： 具有多个处理器核心的数据处理器。 多个处理器核心中的每一个的累积使用信息被存储在数据处理器内的存储设备中，其中累积的使用信息指示多个处理器核心的每个处理器核心的累积使用。 处理器使用累积的使用信息来选择处理器核心来执行处理器操作。
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公开(公告)号：US20130268732A1
公开(公告)日：2013-10-10
申请号：US13440728
申请日：2012-04-05
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.
摘要翻译： 缓存的行通常维持在低功率状态。 响应于存储器访问操作，数据处理器预测可能由操作定向的多个高速缓存行，并且将多个高速缓存行中的每一个转换为活动状态以准备它们进行访问。 基于对基本地址的一部分和偏移的对应部分的推测性解码来预测多个高速缓存行，而不执行部分的完全添加。 由于没有执行完全相加，所以可以以足够的速度执行推测解码，以便在存储器地址的完全解码完成之前允许该组行转换到活动状态。 因此，当解码完成时，与存储器地址相关联的高速缓存行可以进行访问，从而保持高速缓存访问的低延迟。
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公开(公告)号：US20130046928A1
公开(公告)日：2013-02-21
申请号：US13213900
申请日：2011-08-19
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译： 一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126） 不使用操作数加法器的输出和从操作数（111,113）中读出。 将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。 从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。
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公开(公告)号：US08319548B2
公开(公告)日：2012-11-27
申请号：US12622277
申请日：2009-11-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
IPC分类号： G05F1/10
摘要： A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.
摘要翻译： 电压调节器调节节点处的电压，并且具有耦合到节点的电路以向节点提供电流。 耦合在节点和第一电源电压端子之间的调节晶体管具有并联耦合的禁用晶体管，并且通过将第一电源电压端子直接连接到节点来选择性地禁止。 反相级具有连接到调节晶体管的输出端。 负载晶体管具有耦合到第二电源电压端子的第一电流电极和连接在一起并耦合到反相级的输入端的控制电极和第二电流电极。 感测晶体管具有耦合到负载晶体管的第二电流电极的第一电流电极，直接连接到节点的控制电极和耦合到第一电源电压端子的第二电流电极。
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公开(公告)号：US20110116328A1
公开(公告)日：2011-05-19
申请号：US12620314
申请日：2009-11-17
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1075 , G11C7/18 , G11C19/00 , G11C19/28
摘要： An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.
摘要翻译： 存储器位单元阵列可操作以提供具有数据移位能力的存储器件，从而能够以并行和串行方式从存储器件灵活地存储和检索数据。 因此，存储器阵列可以用于常规存储器存储操作，并且还可以用于提供对存储的数据元素的布置的改变的诸如矩阵操作的操作。
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